Cypress CY7C1475BV25, CY7C1471BV25, CY7C1473BV25 manual TAP Registers

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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

TAP Registers

Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry. Only one register is selectable at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block Diagram” on page 13. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts the data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor specific, 32-bit code during the Capture DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page 17.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page 17. Three of these instructions are listed as RESERVED and are not for use. The other five instructions are described in this section in detail.

The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.

You cannot use the TAP controller to load address data or control signals into the SRAM and you cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instruc- tions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller making this device not compliant with 1149.1. The TAP controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor specific, 32-bit code to load into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE for shifting out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.

Be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that, during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is

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Contents Description 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV25 2M x Logic Block Diagram CY7C1473BV25 4M xLogic Block Diagram CY7C1475BV25 1M x Pin Configurations CY7C1471BV25CY7C1473BV25 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV25 2M x CY7C1473BV25 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV25 1M × NC/1GPower Supply for the IO Circuitry Mode Input. Selects the Burst Order of the DevicePower Supply Inputs to the Core of the Device Pin Definitions Name DescriptionName Description Functional OverviewPin Definitions TDIParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsFirst Second Third Fourth Address A1 A0 Used Truth TableOperation Address Truth Table for Read/Write FunctionTAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Timing 5V TAP AC Test Conditions TAP AC Switching CharacteristicsTAP DC Electrical Characteristics And Operating Conditions Scan Register Sizes Register Name Bit Size Identification Codes Instruction DescriptionBit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 1M x Bit # Ball ID Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientParameter Description Test Conditions Tqfp Fbga Unit CapacitanceThermal Resistance Parameter Description 133 MHz 100 MHz Unit Min Max Switching CharacteristicsSetup Times Output TimesRite ReadStall Switching WaveformsAddress ZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document History

CY7C1475BV25, CY7C1473BV25, CY7C1471BV25 specifications

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