Cypress CY7C1473BV25, CY7C1471BV25 manual Features, Selection Guide Functional Description

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CY7C1471BV25

CY7C1473BV25, CY7C1475BV25

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Features

■No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

■Supports up to 133 MHz bus operations with zero wait states

■Data transfers on every clock

■Pin compatible and functionally equivalent to ZBT™ devices

■Internally self timed output buffer control to eliminate the need to use OE

■Registered inputs for flow through operation

■Byte Write capability

■2.5V IO supply (VDDQ)

■Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

■Clock Enable (CEN) pin to enable clock and suspend operation

■Synchronous self timed writes

■Asynchronous Output Enable (OE)

■CY7C1471BV25, CY7C1473BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1475BV25 available in Pb-free and non-Pb-free 209-ball FBGA package.

■Three Chip Enables (CE1, CE2, CE3) for simple depth expansion.

■Automatic power down feature available using ZZ mode or CE deselect.

■IEEE 1149.1 JTAG Boundary Scan compatible

■Burst Capability - linear or interleaved burst order

■Low standby power

Selection Guide

Functional Description

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

For best practice recommendations, refer to the Cypress appli- cation note AN1064, SRAM System Guidelines.

Description

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.5

ns

 

 

 

 

Maximum Operating Current

305

275

mA

 

 

 

 

Maximum CMOS Standby Current

120

120

mA

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 001-15013 Rev. *E

 

Revised February 29, 2008

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Contents Selection Guide Functional Description FeaturesDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1473BV25 4M x Logic Block Diagram CY7C1471BV25 2M xLogic Block Diagram CY7C1475BV25 1M x CY7C1471BV25 Pin ConfigurationsCY7C1473BV25 CY7C1473BV25 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV25 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV25 1M ×Power Supply Inputs to the Core of the Device Mode Input. Selects the Burst Order of the DevicePower Supply for the IO Circuitry Pin Definitions Name DescriptionPin Definitions Functional OverviewName Description TDIFirst Second Third Fourth Address A1 A0 ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Operation Address Truth TableUsed Function Truth Table for Read/WriteIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Registers TAP Timing TAP DC Electrical Characteristics And Operating Conditions TAP AC Switching Characteristics5V TAP AC Test Conditions Identification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 1M x Bit # Ball ID Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceParameter Description Test Conditions Tqfp Fbga Unit Setup Times Switching CharacteristicsParameter Description 133 MHz 100 MHz Unit Min Max Output TimesRead RiteAddress Switching WaveformsStall ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change Date

CY7C1475BV25, CY7C1473BV25, CY7C1471BV25 specifications

Cypress Semiconductor, a leader in specialized memory solutions, offers a range of high-performance SRAM products, including the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25. These devices are designed to provide high-speed data processing capabilities along with impressive power efficiency, making them ideal choices for a variety of applications in telecommunications, networking, automotive, and consumer electronics.

The CY7C1471BV25 features a 1-Mbit density, while the CY7C1473BV25 and CY7C1475BV25 support densities of 3-Mbits and 5-Mbits respectively. All three models utilize a 3.3V power supply, and deliver fast access times of 5 ns (for CY7C1471BV25) and 6 ns (for CY7C1473BV25 and CY7C1475BV25). This rapid access enables quicker data retrieval and overall enhanced system performance.

One of the standout features of these SRAM devices is their asynchronous operation, which allows for straightforward integration into existing systems without the need for complex timing protocols. They can be easily interfaced with various microcontrollers and digital signal processors, providing flexibility and ease of use. Additionally, the devices are available in multiple package options, including the widely used TSOP and BGA formats, enabling designers to choose the best fit for their specific layouts.

In terms of technology, these SRAMs leverage advanced CMOS manufacturing processes, which contribute to their low power consumption and high reliability. With sleep modes and low standby current, they are particularly suited for battery-operated devices that demand energy efficiency.

Cypress products are renowned for their reliability and robustness, ensuring that the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 can withstand the demands of harsh environments and extended usage. The devices also incorporate features such as high-speed data ports, which facilitate bidirectional data flow, making them optimal for both read and write operations.

In summary, the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 SRAMs by Cypress are excellent choices for those seeking high-performance, low-power memory solutions. Their advanced technology, combined with a variety of features and options, caters to the needs of many industries, paving the way for innovative designs in modern electronics.
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