Cypress CY7C1471BV25, CY7C1473BV25, CY7C1475BV25 manual TAP Timing

Page 15

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct signal value, make certain that the SRAM signal is stabi- lized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH).

The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not imple- mented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Figure 5. TAP Timing

1

 

2

 

 

 

 

 

 

Test Clock

 

 

 

 

 

 

 

(TCK )

 

 

tTH

 

 

 

 

 

 

 

 

 

 

 

tTM SS

 

tTM SH

 

 

 

 

 

 

 

 

 

Test M ode Select (TM S)

tTDIS tTDIH

Test Data-In (TDI)

Test Data-Out (TDO)

3

4

5

6

tTL

tCY C

 

 

tTDO V

tTDOX

DON’T CA RE

UNDEFINED

Document #: 001-15013 Rev. *E

Page 15 of 30

[+] Feedback

Page 14 Page 16
Image 15
Page 14 Page 16
Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 100 MHz UnitLogic Block Diagram CY7C1473BV25 4M x Logic Block Diagram CY7C1471BV25 2M xLogic Block Diagram CY7C1475BV25 1M x CY7C1471BV25 Pin ConfigurationsCY7C1473BV25 CY7C1473BV25 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV25 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV25 1M ×Pin Definitions Name Description Mode Input. Selects the Burst Order of the DevicePower Supply Inputs to the Core of the Device Power Supply for the IO CircuitryTDI Functional OverviewPin Definitions Name DescriptionZZ Mode Electrical Characteristics First Second Third Fourth Address A1 A0Parameter Description Test Conditions Min Max Unit Truth Table Operation AddressUsed Function Truth Table for Read/WriteIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Registers TAP Timing TAP AC Switching Characteristics TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 2M x Bit # Ball ID Boundary Scan Exit Order 4M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 1M x Bit # Ball ID Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceParameter Description Test Conditions Tqfp Fbga Unit Output Times Switching CharacteristicsSetup Times Parameter Description 133 MHz 100 MHz Unit Min MaxRead RiteSwitching Waveforms AddressStall ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change Date

CY7C1475BV25, CY7C1473BV25, CY7C1471BV25 specifications

Cypress Semiconductor, a leader in specialized memory solutions, offers a range of high-performance SRAM products, including the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25. These devices are designed to provide high-speed data processing capabilities along with impressive power efficiency, making them ideal choices for a variety of applications in telecommunications, networking, automotive, and consumer electronics.

The CY7C1471BV25 features a 1-Mbit density, while the CY7C1473BV25 and CY7C1475BV25 support densities of 3-Mbits and 5-Mbits respectively. All three models utilize a 3.3V power supply, and deliver fast access times of 5 ns (for CY7C1471BV25) and 6 ns (for CY7C1473BV25 and CY7C1475BV25). This rapid access enables quicker data retrieval and overall enhanced system performance.

One of the standout features of these SRAM devices is their asynchronous operation, which allows for straightforward integration into existing systems without the need for complex timing protocols. They can be easily interfaced with various microcontrollers and digital signal processors, providing flexibility and ease of use. Additionally, the devices are available in multiple package options, including the widely used TSOP and BGA formats, enabling designers to choose the best fit for their specific layouts.

In terms of technology, these SRAMs leverage advanced CMOS manufacturing processes, which contribute to their low power consumption and high reliability. With sleep modes and low standby current, they are particularly suited for battery-operated devices that demand energy efficiency.

Cypress products are renowned for their reliability and robustness, ensuring that the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 can withstand the demands of harsh environments and extended usage. The devices also incorporate features such as high-speed data ports, which facilitate bidirectional data flow, making them optimal for both read and write operations.

In summary, the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 SRAMs by Cypress are excellent choices for those seeking high-performance, low-power memory solutions. Their advanced technology, combined with a variety of features and options, caters to the needs of many industries, paving the way for innovative designs in modern electronics.
Top Page Image Contents