Cypress CY7C1561V18, CY7C1576V18 TAP Controller Block Diagram, TAP Electrical Characteristics

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

TAP Controller Block Diagram


																						0
																						0

																			Bypass Register

TDI						Selection													2	1		0					Selection
																			2	1		0

														Instruction Register
						Circuitry								Instruction Register
																											Circuitry
												31		30	29	.	.		2	1		0					Circuitry



														Identification Register

												108		.	.	.	.		2	1		0



														Boundary Scan Register

	TCK

																TAP Controller

	TMS
	TMS

TDO

TAP Electrical Characteristics

Over the Operating Range [13, 14, 15]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	–5	5	μA

Notes

13.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

14.Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).

15.All Voltage referenced to Ground.

Document Number: 001-05384 Rev. *F

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Contents Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Features ConfigurationsSelection Guide Functional DescriptionLogic Block Diagram CY7C1561V18 Logic Block Diagram CY7C1576V18Doff Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18CY7C1576V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1561V18 8M xCY7C1563V18 4M x WPS BWSCY7C1565V18 2M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsProgrammable Impedance Valid Data Indicator QvldApplication Example Depth ExpansionComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1576V18 followsWrite cycle description table for CY7C1565V18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings Current Both Ports Deselected Automatic Power down Max VDD 400 MHzVDD Operating Supply VDD = Max 333 MHz 300 MHzParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceHigh Switching CharacteristicsConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History