Cypress CY7C1576V18 manual Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1561V18 8M x

Page 4

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Pin Configuration

The pin configuration for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follow. [2]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1561V18 (8M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

1

NC/144M

A

A

CQ

CQ

WPS

NWS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

QVLD

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1576V18 (8M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

NC

NC/144M

A

A

CQ

CQ

WPS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

QVLD

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-05384 Rev. *F

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Contents Features Configurations Selection GuideFunctional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1576V18 Logic Block Diagram CY7C1561V18Doff Logic Block Diagram CY7C1563V18 Logic Block Diagram CY7C1565V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1561V18 8M x CY7C1576V18 8M xWPS BWS CY7C1563V18 4M xCY7C1565V18 2M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Application ExampleDepth Expansion Programmable ImpedanceTruth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1576V18 follows Write cycle description table for CY7C1565V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Automatic Power down Max VDD 400 MHz VDD Operating Supply VDD = Max 333 MHz300 MHz Current Both Ports DeselectedAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitSwitching Characteristics Consortium Description 400 MHz 375 MHz 333 MHz 300 MHz UnitParameter Min Max HighSwitching Waveforms Read/Write/Deselect Sequence 31, 32Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History