Cypress CY7C1563V18, CY7C1576V18 Capacitance, Thermal Resistance, AC Electrical Characteristics

Page 22

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

AC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V

5

pF

CCLK

Clock Input Capacitance

 

6

pF

CO

Output Capacitance

 

7

pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Unit

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test methods and

11.82

°C/W

 

(Junction to Ambient)

procedures for measuring thermal impedance, in

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

2.33

°C/W

 

 

(Junction to Case)

 

 

 

Figure 4. AC Test Loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES[23]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

23.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.

Document Number: 001-05384 Rev. *F

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Contents Functional Description Features ConfigurationsSelection Guide Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1576V18 Logic Block Diagram CY7C1561V18Doff Logic Block Diagram CY7C1563V18 Logic Block Diagram CY7C1565V18CY7C1561V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1576V18 8M xWPS BWS CY7C1563V18 4M xCY7C1565V18 2M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldApplication Example Programmable ImpedanceOperation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1576V18 followsWrite cycle description table for CY7C1565V18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings 300 MHz Automatic Power down Max VDD 400 MHzVDD Operating Supply VDD = Max 333 MHz Current Both Ports DeselectedThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit HighSwitching Waveforms Read/Write/Deselect Sequence 31, 32Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History