Cypress CY7C1565V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1561V18	CY7C1576V18	CY7C1563V18	CY7C1565V18	Description
		CY7C1561V18	CY7C1576V18	CY7C1563V18	CY7C1565V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010010001000100	11010010001001100	11010010001010100	11010010001100100	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document Number: 001-05384 Rev. *F

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Contents Selection Guide Features ConfigurationsFunctional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitDoff Logic Block Diagram CY7C1561V18Logic Block Diagram CY7C1576V18 Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1561V18 8M x CY7C1576V18 8M xCY7C1565V18 2M x CY7C1563V18 4M xWPS BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsApplication Example Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1565V18 follows Write cycle description table for CY7C1576V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics VDD Operating Supply VDD = Max 333 MHz Automatic Power down Max VDD 400 MHz300 MHz Current Both Ports DeselectedCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History