Cypress CY7C1563V18 manual Pin Definitions, Pin Name Pin Description, Negative Input Clock Input

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CY7C1561V18, CY7C1576V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1563V18, CY7C1565V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

 

Pin Description

 

D[x:0]

Input-

Data Input Signals. Sampled on the rising edge of K and

 

clocks when valid write operations are active.

K

 

 

 

 

 

 

 

Synchronous

CY7C1561V18 − D[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1576V18 − D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1563V18 − D[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1565V18 − D[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

 

WPS

 

 

 

 

 

 

 

Synchronous

write operation is initiated. Deasserting deselects the Write Port. Deselecting the write port ignores D[x:0].

 

 

 

 

 

 

0,

Input-

Nibble Write Select 0, 1− Active LOW (CY7C1561V18 Only). Sampled on the rising edge of the K and

 

NWS

 

NWS1,

Synchronous

K clocks when write operations are active. Used to select which nibble is written into the device during

 

 

 

 

 

 

 

 

the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

 

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

 

 

 

 

 

 

 

 

ignores the corresponding nibble of data and it is not written into the device.

 

 

 

 

 

0,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

 

clocks when

 

BWS

K

 

BWS1,

Synchronous

write operations are active. Used to select which byte is written into the device during the current portion

 

BWS2,

 

of the write operations. Bytes not written remain unaltered.

 

BWS3

 

CY7C1576V18 − BWS0

controls D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1563V18 − BWS0

controls D[8:0] and BWS1 controls D[17:9].

 

 

 

 

 

 

 

 

CY7C1565V18 − BWS0

controls D[8:0], BWS1 controls D[17:9],

 

 

 

 

 

 

 

 

BWS2 controls D[26:18] and BWS3 controls D[35:27].

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

 

ignores the corresponding byte of data and it is not written into the device.

 

A

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

 

 

 

 

 

 

 

Synchronous

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

 

 

 

 

 

 

 

 

8M x 8 (4 arrays each of 2M x 8) for CY7C1561V18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1576V18,

 

 

 

 

 

 

 

 

4M x 18 (4 arrays each of 1M x 18) for CY7C1563V18 and 2M x 36 (4 arrays each of 512K x 36) for

 

 

 

 

 

 

 

 

CY7C1565V18. Therefore, only 21 address inputs are needed to access the entire memory array of

 

 

 

 

 

 

 

 

CY7C1561V18 and CY7C1576V18, 20 address inputs for CY7C1563V18, and 19 address inputs for

 

 

 

 

 

 

 

 

CY7C1565V18. These inputs are ignored when the appropriate port is deselected.

 

Q[x:0]

Outputs-

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is

 

 

 

 

 

 

 

Synchronous

driven out on the rising edge of both the K and K clocks during read operations. On deselecting the read

 

 

 

 

 

 

 

 

port, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

 

CY7C1561V18 − Q[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1576V18 − Q[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1563V18 − Q[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1565V18 − Q[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

 

RPS

 

 

 

 

 

 

 

Synchronous

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

 

 

 

 

 

 

 

 

allowed to complete and the output drivers are automatically tri-stated following the next rising edge of

 

 

 

 

 

 

 

 

the K clock. Each read access consists of a burst of four sequential transfers.

 

QVLD

Valid output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

 

 

 

CQ.

 

 

 

 

 

 

 

indicator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

Input-

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

 

 

 

 

 

 

 

Clock

and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.

 

 

 

 

Input-

Negative Input Clock Input.

 

is used to capture synchronous inputs being presented to the device and

 

K

K

 

 

 

 

 

 

 

Clock

to drive out data through Q[x:0].

 

CQ

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

 

 

 

 

 

 

 

 

(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.

 

 

 

 

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

 

CQ

 

 

 

 

 

 

 

 

(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.

Document Number: 001-05384 Rev. *F

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Contents Functional Description Features ConfigurationsSelection Guide Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1561V18 Logic Block Diagram CY7C1576V18Doff Logic Block Diagram CY7C1563V18 Logic Block Diagram CY7C1565V18CY7C1561V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1576V18 8M xCY7C1563V18 4M x WPS BWSCY7C1565V18 2M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldApplication Example Programmable ImpedanceOperation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1576V18 followsWrite cycle description table for CY7C1565V18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings 300 MHz Automatic Power down Max VDD 400 MHzVDD Operating Supply VDD = Max 333 MHz Current Both Ports DeselectedThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit HighSwitching Waveforms Read/Write/Deselect Sequence 31, 32Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History
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