Cypress CY7C1561V18, CY7C1576V18 Logic Block Diagram CY7C1563V18, Logic Block Diagram CY7C1565V18

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CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Logic Block Diagram (CY7C1563V18)

D[17:0]

20Address

A(19:0) Register

K CLK

Gen.

DOFF

VREF
		Control


WPS
WPS		Logic
		Logic
BWS
BWS	[1:0]

Write Write Write Write Reg Reg Reg Reg

Write Add. Decode	1M x 18 Array	1M x 18 Array	1M x 18 Array	1M x 18 Array
	Read Data Reg.
		72	36
			36
			36

Read Add. Decode

Reg.

Address

A(19:0)

Control

RPS

Logic

Reg.

Q[17:0]

QVLD

Logic Block Diagram (CY7C1565V18)

D[35:0]

19Address

A(18:0) Register

K CLK

Gen.

DOFF

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
	Reg	Reg	Reg	Reg

Decode	512K x	512K x	512K x	512K x	Decode


Write Add.	36 Array	36 Array	36 Array	36 Array	Read Add.
Write Add.	36 Array	36 Array	36 Array	36 Array	Read Add.
	Read Data Reg.

Address Register

Control

Logic

19 A(18:0)

RPS

VREF
		Control


WPS
WPS		Logic
		Logic
BWS
BWS	[3:0]

144

					CQ
		36		CQ

Reg.	Reg.


		36	36



Reg.		36		Q[35:0]
Reg.		36		Q[35:0]
		36		QVLD

Document Number: 001-05384 Rev. *F

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Contents Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Features ConfigurationsSelection Guide Functional DescriptionLogic Block Diagram CY7C1561V18 Logic Block Diagram CY7C1576V18Doff Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18CY7C1576V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1561V18 8M xCY7C1563V18 4M x WPS BWSCY7C1565V18 2M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsProgrammable Impedance Valid Data Indicator QvldApplication Example Depth ExpansionComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1576V18 followsWrite cycle description table for CY7C1565V18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings Current Both Ports Deselected Automatic Power down Max VDD 400 MHzVDD Operating Supply VDD = Max 333 MHz 300 MHzParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceHigh Switching CharacteristicsConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History