Cypress CY7C1576V18, CY7C1565V18 manual Switching Waveforms, Read/Write/Deselect Sequence 31, 32

Page 24

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Switching Waveforms

Read/Write/Deselect Sequence [31, 32, 33]

Figure 5. Waveform for 2.5 Cycle Read Latency

NOP 1

tKH

	READ	WRITE	READ	WRITE	NOP
	2	3	4	5	6	7	8
tKL	tCYC	tKHKH

RPS
tSC tHC	t SC tHC

WPS

D QVLD

A0	A1	A2		A3
tSA tHA		tHD		tSD		tHD
		t SD		tSD
		D10	D11	D12	D13	D30	D31	D32	D33
									tQVLD
				tCO		tDOH			tCQDOH	tCHZ
		tCLZ		tCO		tCQD			tCQDOH
		tCLZ				tCQD

(Read Latency = 2.5 Cycles)

Q00Q01 Q02 Q03 Q20

t CCQO

CQOH

Q21 Q22Q23

tCQH

tCQHCQH

tCQOH

CCQO

DON’T CARE

UNDEFINED

Notes

31.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

32.Outputs are disabled (High-Z) one clock cycle after a NOP.

33.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-05384 Rev. *F

Page 24 of 28

[+] Feedback

Image 24

Contents Features Configurations Selection GuideFunctional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1561V18 Logic Block Diagram CY7C1576V18Doff Logic Block Diagram CY7C1563V18 Logic Block Diagram CY7C1565V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1561V18 8M x CY7C1576V18 8M xCY7C1563V18 4M x WPS BWSCY7C1565V18 2M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Application ExampleDepth Expansion Programmable ImpedanceTruth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1576V18 follows Write cycle description table for CY7C1565V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings Automatic Power down Max VDD 400 MHz VDD Operating Supply VDD = Max 333 MHz300 MHz Current Both Ports DeselectedAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitSwitching Characteristics Consortium Description 400 MHz 375 MHz 333 MHz 300 MHz UnitParameter Min Max HighSwitching Waveforms Read/Write/Deselect Sequence 31, 32Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History