Cypress CY7C1561V18, CY7C1576V18, CY7C1565V18 Power Up Sequence in QDR-II+ Sram, DLL Constraints

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Power Up Sequence in QDR-II+ SRAM

QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Power Up Sequence

■Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency.

■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL.

K

K

VDD/VDDQ

DOFF

Figure 3. Power Up Waveforms

~ ~

	~ ~

Unstable Clock	> 2048 Stable Clock	Start Normal
Clock Start (Clock Starts after VDD/VDDQ is Stable)		Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

Fix HIGH (tie to VDDQ)

Document Number: 001-05384 Rev. *F

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Contents Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Features ConfigurationsSelection Guide Functional DescriptionLogic Block Diagram CY7C1576V18 Logic Block Diagram CY7C1561V18Doff Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18CY7C1576V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1561V18 8M xWPS BWS CY7C1563V18 4M xCY7C1565V18 2M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsProgrammable Impedance Valid Data Indicator QvldApplication Example Depth ExpansionComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1576V18 followsWrite cycle description table for CY7C1565V18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Current Both Ports Deselected Automatic Power down Max VDD 400 MHzVDD Operating Supply VDD = Max 333 MHz 300 MHzParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceHigh Switching CharacteristicsConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History