Cypress CY7C1565V18, CY7C1576V18, CY7C1563V18, CY7C1561V18 manual Ordering Information

Page 25

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
400	CY7C1561V18-400BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1576V18-400BZC

	CY7C1563V18-400BZC

	CY7C1565V18-400BZC

	CY7C1561V18-400BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1576V18-400BZXC

	CY7C1563V18-400BZXC

	CY7C1565V18-400BZXC

	CY7C1561V18-400BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1576V18-400BZI

	CY7C1563V18-400BZI

	CY7C1565V18-400BZI

	CY7C1561V18-400BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1576V18-400BZXI

	CY7C1563V18-400BZXI

	CY7C1565V18-400BZXI

375	CY7C1561V18-375BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1576V18-375BZC

	CY7C1563V18-375BZC

	CY7C1565V18-375BZC

	CY7C1561V18-375BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1576V18-375BZXC

	CY7C1563V18-375BZXC

	CY7C1565V18-375BZXC

	CY7C1561V18-375BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1576V18-375BZI

	CY7C1563V18-375BZI

	CY7C1565V18-375BZI

	CY7C1561V18-375BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1576V18-375BZXI

	CY7C1563V18-375BZXI

	CY7C1565V18-375BZXI

Document Number: 001-05384 Rev. *F

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Contents Selection Guide Features ConfigurationsFunctional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1576V18 Logic Block Diagram CY7C1561V18Doff Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1561V18 8M x CY7C1576V18 8M xWPS BWS CY7C1563V18 4M xCY7C1565V18 2M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsApplication Example Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1565V18 follows Write cycle description table for CY7C1576V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings VDD Operating Supply VDD = Max 333 MHz Automatic Power down Max VDD 400 MHz300 MHz Current Both Ports DeselectedCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitConsortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History