Cypress CY7C1387DV25 Partial Truth Table for Read/Write 5, Function CY7C1386DV25/CY7C1386FV25

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Partial Truth Table for Read/Write [5, 10]

Function (CY7C1386DV25/CY7C1386FV25)

GW

BWE

BWD

BWC

BWB

BWA

Read

H

H

X

X

X

X

Read

H

L

H

H

H

H

Write Byte A – (DQA and DQPA)

H

L

H

H

H

L

Write Byte B – (DQB and DQPB)

H

L

H

H

L

H

Write Bytes B, A

H

L

H

H

L

L

Write Byte C – (DQC and DQPC)

H

L

H

L

H

H

Write Bytes C, A

H

L

H

L

H

L

Write Bytes C, B

H

L

H

L

L

H

Write Bytes C, B, A

H

L

H

L

L

L

Write Byte D – (DQD and DQPD)

H

L

L

H

H

H

Write Bytes D, A

H

L

L

H

H

L

Write Bytes D, B

H

L

L

H

L

H

Write Bytes D, B, A

H

L

L

H

L

L

Write Bytes D, C

H

L

L

L

H

H

Write Bytes D, C, A

H

L

L

L

H

L

Write Bytes D, C, B

H

L

L

L

L

H

Write All Bytes

H

L

L

L

L

L

Write All Bytes

L

X

X

X

X

X

Truth Table for Read/Write [5, 10]

Function (CY7C1387DV25/CY7C1387FV25)

GW

BWE

BWB

BWA

Read

H

H

X

X

Read

H

L

H

H

Write Byte A – (DQA and DQPA)

H

L

H

L

Write Byte B – (DQB and DQPB)

H

L

L

H

Write All Bytes

H

L

L

L

Write All Bytes

L

X

X

X

Note

10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid appropriate write will be done based on which byte write is active.

Document Number: 38-05548 Rev. *E

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xCY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Function CY7C1386DV25/CY7C1386FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1387DV25/CY7C1387FV25TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Output Load Equivalent TAP AC Switching CharacteristicsTAP AC Test Conditions Parameter Description Min Max Unit ClockIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance PackageParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching CharacteristicsSetup Times Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History