Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25, CY7C1386FV25 manual TAP Timing, Bypass

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CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

Test Clock

 

(TCK)

tTH

 

tTMSS

tTMSH

Test Mode Select

 

(TMS)

 

tTDIS

tTDIH

Test Data-In

 

(TDI)

 

Test Data-Out

 

(TDO)

 

3

4

5

6

tTL tCYC

tTDOV

tTDOX

DON’T CARE

UNDEFINED

Document Number: 38-05548 Rev. *E

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xCY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5 Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction RegisterBypass TAP TimingTAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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