Cypress CY7C1387DV25, CY7C1387FV25, CY7C1386DV25 manual Pin Configurations Ball BGA 1 Chip Enable

Page 4

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Pin Configurations (continued)

119-Ball BGA (1 Chip Enable)

CY7C1386FV25 (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

B

DQB

DQB

BW

ADV

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

BWE

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1387FV25 (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

NC

NC

DQA

BW

ADV

H

DQB

NC

VSS

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

NC

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document Number: 38-05548 Rev. *E

Page 4 of 30

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Contents Features Selection Guide 250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xCY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Power supply inputs to the core of the device Pin DefinitionsName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Partial Truth Table for Read/Write 5 Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics TAP AC Test ConditionsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageSwitching Characteristics Setup TimesParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History