Cypress CY7C1386FV25 manual Capacitance, Thermal Resistance, AC Test Loads and Waveforms, Package

Page 19

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Capacitance [19]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Package	Package	Package	Unit
				Package	Package	Package

	CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	8	9	pF
			VDD/VDDQ = 2.5V
	CCLK	Clock Input Capacitance	VDD/VDDQ = 2.5V	5	8	9	pF
	CCLK	Clock Input Capacitance		5	8	9	pF
	CIO	Input/Output Capacitance		5	8	9	pF

Thermal Resistance [19]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Package	Package	Package	Unit
				Package	Package	Package

	ΘJA	Thermal Resistance	Test conditions follow standard	28.66	23.8	20.7	°C/W
		(Junction to Ambient)	test methods and procedures
			for measuring thermal
	ΘJC	Thermal Resistance	for measuring thermal	4.08	6.2	4.0	°C/W
	ΘJC	Thermal Resistance	impedance, per EIA/JESD51.	4.08	6.2	4.0	°C/W
		(Junction to Case)

AC Test Loads and Waveforms

2.5V IO Test Load

OUTPUT

2.5V

R = 1667Ω

ALL INPUT PULSES

VDDQ

Z0

= 50Ω

OUTPUT

RL = 50Ω

10%

90%

5 pF

R = 1538Ω

GND

≤ 1 ns

VT = 1.25V

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

90%

10%

≤ 1 ns

Note

19. Tested initially and after any design or process change that may affect these parameters.

Document Number: 38-05548 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xCY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Byte write select inputs, active LOW. Qualified with Power supply inputs to the core of the devicePin Definitions Name DescriptionFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Function CY7C1387DV25/CY7C1387FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1386DV25/CY7C1386FV25TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction RegisterBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsTAP AC Test Conditions TAP AC Output Load EquivalentRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Bit # Ball ID Ball BGA Boundary Scan Order 14A11 Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangePackage CapacitanceThermal Resistance AC Test Loads and WaveformsOutput Times Switching CharacteristicsSetup Times Parameter Description 250 MHz 200 MHz 167 MHz Unit Min MaxRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change