Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25, CY7C1386FV25 manual A11

Page 17

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

165-Ball BGA Boundary Scan Order [14, 16]

Bit #

Ball ID

 

Bit #

Ball ID

 

Bit #

Ball ID

1

N6

 

31

D10

 

61

G1

 

 

 

 

 

 

 

 

2

N7

 

32

C11

 

62

D2

 

 

 

 

 

 

 

 

3

N10

 

33

A11

 

63

E2

 

 

 

 

 

 

 

 

4

P11

 

34

B11

 

64

F2

 

 

 

 

 

 

 

 

5

P8

 

35

A10

 

65

G2

 

 

 

 

 

 

 

 

6

R8

 

36

B10

 

66

H1

 

 

 

 

 

 

 

 

7

R9

 

37

A9

 

67

H3

 

 

 

 

 

 

 

 

8

P9

 

38

B9

 

68

J1

 

 

 

 

 

 

 

 

9

P10

 

39

C10

 

69

K1

 

 

 

 

 

 

 

 

10

R10

 

40

A8

 

70

L1

 

 

 

 

 

 

 

 

11

R11

 

41

B8

 

71

M1

 

 

 

 

 

 

 

 

12

H11

 

42

A7

 

72

J2

 

 

 

 

 

 

 

 

13

N11

 

43

B7

 

73

K2

 

 

 

 

 

 

 

 

14

M11

 

44

B6

 

74

L2

 

 

 

 

 

 

 

 

15

L11

 

45

A6

 

75

M2

 

 

 

 

 

 

 

 

16

K11

 

46

B5

 

76

N1

 

 

 

 

 

 

 

 

17

J11

 

47

A5

 

77

N2

 

 

 

 

 

 

 

 

18

M10

 

48

A4

 

78

P1

 

 

 

 

 

 

 

 

19

L10

 

49

B4

 

79

R1

 

 

 

 

 

 

 

 

20

K10

 

50

B3

 

80

R2

 

 

 

 

 

 

 

 

21

J10

 

51

A3

 

81

P3

 

 

 

 

 

 

 

 

22

H9

 

52

A2

 

82

R3

 

 

 

 

 

 

 

 

23

H10

 

53

B2

 

83

P2

 

 

 

 

 

 

 

 

24

G11

 

54

C2

 

84

R4

 

 

 

 

 

 

 

 

25

F11

 

55

B1

 

85

P4

 

 

 

 

 

 

 

 

26

E11

 

56

A1

 

86

N5

 

 

 

 

 

 

 

 

27

D11

 

57

C1

 

87

P6

 

 

 

 

 

 

 

 

28

G10

 

58

D1

 

88

R6

 

 

 

 

 

 

 

 

29

F10

 

59

E1

 

89

Internal

 

 

 

 

 

 

 

 

30

E10

 

60

F1

 

 

 

 

 

 

 

 

 

 

 

Note

16. Bit #89 is preset HIGH.

Document Number: 38-05548 Rev. *E

Page 17 of 30

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xCY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDOperation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction RegisterBypass TAP TimingTAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change