Cypress CY7C1386FV25, CY7C1387DV25 manual Identification Register Definitions, Scan Register Sizes

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Identification Register Definitions

	Instruction Field	CY7C1386DV25/	CY7C1387DV25/	Description
	Instruction Field	CY7C1386FV25	CY7C1387FV25	Description
		CY7C1386FV25	CY7C1387FV25

	Revision Number (31:29)	000	000	Describes the version number.

	Device Depth (28:24)	01011	01011	Reserved for internal use

	Device Width (23:18) 119-BGA	101110	101110	Defines the memory type and
				architecture.
	Device Width (23:18) 165-FBGA	000110	000110	Defines the memory type and
				architecture.
	Cypress Device ID (17:12)	100101	010101	Defines the width and density

	Cypress JEDEC ID Code (11:1)	00000110100	00000110100	Allows unique identification of SRAM
				vendor.
	ID Register Presence Indicator (0)	1	1	Indicates the presence of an ID register.

Scan Register Sizes

Register Name	Bit Size (x18)	Bit Size (x36)
Instruction	3	3

Bypass	1	1

ID	32	32

Boundary Scan Order (119-ball BGA package)	85	85

Boundary Scan Order (165-ball fBGA package)	89	89

Identification Codes

Instruction	Code	Description

EXTEST	000	Captures IO ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM outputs to High-Z state.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and
		TDO. This operation does not affect SRAM operations.
SAMPLE Z	010	Captures IO ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures IO ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect SRAM operation.
RESERVED	101	Do Not Use. This instruction is reserved for future use.

RESERVED	110	Do Not Use. This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operations.

Document Number: 38-05548 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xPin Configurations CY7C1386DV25 512K XCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Byte write select inputs, active LOW. Qualified with Power supply inputs to the core of the devicePin Definitions Name DescriptionFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitOperation Add. Used Function CY7C1387DV25/CY7C1387FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1386DV25/CY7C1386FV25TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction RegisterBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsTAP AC Test Conditions TAP AC Output Load EquivalentRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A11 Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangePackage CapacitanceThermal Resistance AC Test Loads and WaveformsOutput Times Switching CharacteristicsSetup Times Parameter Description 250 MHz 200 MHz 167 MHz Unit Min MaxRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change