Cypress CY7C1386DV25 manual TAP AC Switching Characteristics, TAP AC Test Conditions, Hold Times

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

TAP AC Switching Characteristics

Over the Operating Range [11, 12]

Parameter	Description	Min.	Max.	Unit
Clock

tTCYC	TCK Clock Cycle Time	50		ns
tTF	TCK Clock Frequency		20	MHz
tTH	TCK Clock HIGH time	20		ns
tTL	TCK Clock LOW time	20		ns
Output Times
tTDOV	TCK Clock LOW to TDO Valid		10	ns
tTDOX	TCK Clock LOW to TDO Invalid	0		ns
Setup Times
tTMSS	TMS Setup to TCK Clock Rise	5		ns
tTDIS	TDI Setup to TCK Clock Rise	5		ns
tCS	Capture Setup to TCK Rise	5		ns
Hold Times

tTMSH	TMS Hold after TCK Clock Rise	5		ns
tTDIH	TDI Hold after Clock Rise	5		ns
tCH	Capture Hold after Clock Rise	5		ns

TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

TAP AC Output Load Equivalent

1.25V

50Ω

TDO

ZO= 50 Ω						20pF
ZO= 50 Ω						20pF

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 2.5V ±0.165V unless otherwise noted) [13]

Parameter	Description	Test Conditions	Min.	Max.	Unit
VOH1	Output HIGH Voltage	IOH = –1.0 mA	1.7		V
VOH2	Output HIGH Voltage	IOH = –100 µA	2.1		V
VOL1	Output LOW Voltage	IOL = 1.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 µA		0.2	V
VIH	Input HIGH Voltage		1.7	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.7	V
IX	Input Load Current	GND < VIN < VDDQ	–5	5	µA

Note

11.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

12.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1ns.

13.All voltages referenced to VSS (GND).

Document Number: 38-05548 Rev. *E

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xCY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDOperation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1386DV25/CY7C1386FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1387DV25/CY7C1387FV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Output Load Equivalent TAP AC Switching CharacteristicsTAP AC Test Conditions Parameter Description Min Max Unit ClockIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance PackageParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching CharacteristicsSetup Times Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History