Cypress CY7C1386DV25 Maximum Ratings, Operating Range, Electrical Characteristics, Range Ambient

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC Voltage Applied to Outputs	–0.5V to VDDQ + 0.5V
in Tri-State

DC Input Voltage	–0.5V to VDD + 0.5V
Current into Outputs (LOW)	20 mA
Static Discharge Voltage	>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current	>200 mA

Operating Range

Range	Ambient	VDD	VDDQ
	Temperature
Commercial	0°C to +70°C	2.5V ±5%	2.5V –5%
			to VDD
Industrial	–40°C to +85°C

Electrical Characteristics

Over the Operating Range [17, 18]

Parameter		Description	Test Conditions		Min.	Max.	Unit
VDD		Power Supply Voltage			2.375	2.625	V
VDDQ		IO Supply Voltage	for 2.5V IO		2.375	VDD	V
VOH		Output HIGH Voltage	for 2.5V IO, IOH = –1.0 mA		2.0		V
VOL		Output LOW Voltage	for 2.5V IO, IOL = 1.0 mA			0.4	V
V	IH	Input HIGH Voltage [17]	for 2.5V IO		1.7	V + 0.3V	V
						DD
VIL		Input LOW Voltage [17]	for 2.5V IO		–0.3	0.7	V
IX		Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	µA
		except ZZ and MODE
		Input Current of MODE	Input = VSS		–30		µA
			Input = VDD			5	µA
		Input Current of ZZ	Input = VSS		–5		µA
			Input = VDD			30	µA
IOZ		Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	µA
IDD		VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4.0-ns cycle, 250 MHz		350	mA
		Current	f = fMAX = 1/tCYC
				5-ns cycle, 200 MHz		300	mA
				6-ns cycle, 167 MHz		275	mA
ISB1		Automatic CE	VDD = Max, Device Deselected,	4.0-ns cycle, 250 MHz		160	mA
		Power Down	VIN ≥ VIH or VIN ≤ VIL
				5-ns cycle, 200 MHz		150	mA
		Current—TTL Inputs	f = fMAX = 1/tCYC
				6-ns cycle, 167 MHz		140	mA
ISB2		Automatic CE	VDD = Max, Device Deselected,	All speeds		70	mA
		Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
		Current—CMOS Inputs	f = 0
ISB3		Automatic CE	VDD = Max, Device Deselected,	4.0-ns cycle, 250 MHz		135	mA
		Power Down	or VIN ≤ 0.3V or VIN > VDDQ – 0.3V
				5-ns cycle, 200 MHz		130	mA
		Current—CMOS Inputs	f = fMAX = 1/tCYC
				6-ns cycle, 167 MHz		125	mA
ISB4		Automatic CE	VDD = Max, Device Deselected,	All Speeds		80	mA
		Power Down	VIN ≥ VIH or VIN ≤ VIL, f = 0
		Current—TTL Inputs

Notes

17.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).

18.Tpower up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document Number: 38-05548 Rev. *E Page 18 of 30

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