Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25 Soldernotespad Type NON-SOLDER Mask Defined Nsmd

Page 29

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Package Diagrams (continued)

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

TOP VIEW

 

 

 

 

 

 

TOP VIEW

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

BOTTOM VIEW

BOTTOM VIEWPIN 1 CORNER

PIN 1 CORNER

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

Ø0.50

-0Ø0.06

.25 M C A B

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

+0.14

-0.06

 

11

10

9

8

7

6

5

Ø0.50

(165X)

4

3

2

1

 

 

 

 

 

 

 

 

 

+0.14

 

15.00±0.10

15.00±0.10

A

1

2

3

4

5

6

7

8

9

10

11

B

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CB

DC

ED

FE

GF

H

G

15.00±0.10

 

 

J

H

 

K

J

 

 

 

LK

ML

NM

PN

RP R

14.00 15.00±0.10

1.00

7.0014.00

1.00

7.00

11

10

9

8

7

6

5

4

3

2

1A

BA

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP

R

A

0.25 C

A

0.3600.25.3±0C .05

A

B

13.00±0.10

 

 

B

13.00±0.10

 

 

0.53±0.05

1.40 MAX.

0.15 C 1.40 MAX.

0.15 C

C

SEATING PLANE

 

 

SEATING PLANE

 

 

 

 

 

0.36

C

 

 

0.35±0.06

0.35±0.06

 

 

1.00

A

5.00

1.00

 

5.00

 

10.00

 

10.00

B

13.00±0.10

B

13.00±0.10

0.15(4X)

 

0.15(4X)

 

NOTES :

 

SOLDERNOTESPAD TYPE: : NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document Number: 38-05548 Rev. *E

Page 29 of 30

© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

Page 28 Page 30
Image 29
Page 28 Page 30
Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xCY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDOperation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction RegisterBypass TAP TimingTAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
Top Page Image Contents