Cypress CY7C1387FV25, CY7C1387DV25 manual ZZ Mode Electrical Characteristics, Operation Add. Used

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

ZZ Mode Electrical Characteristics

Parameter

 

Description

 

 

 

 

 

 

 

Test Conditions

 

 

 

Min.

 

 

Max.

 

Unit

IDDZZ

 

Sleep mode standby current

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

80

 

mA

tZZS

 

Device operation to ZZ

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

2tCYC

 

ns

tZZREC

 

ZZ recovery time

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

2tCYC

 

 

 

 

 

 

ns

tZZI

 

ZZ Active to sleep current

 

 

 

 

 

This parameter is sampled

 

 

 

 

 

 

 

2tCYC

 

ns

tRZZI

 

ZZ Inactive to exit sleep current

 

 

 

This parameter is sampled

 

0

 

 

 

 

 

 

 

ns

Truth Table [4, 5, 6, 7, 8, 9]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Add. Used

 

CE

1

CE2

 

CE

3

ZZ

 

ADSP

 

 

ADSC

 

 

ADV

 

 

WRITE

 

 

 

OE

 

CLK

DQ

Deselect Cycle, Power Down

None

 

H

X

 

X

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power Down

None

 

X

X

 

X

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

4.X = Don't Care, H = Logic HIGH, L = Logic LOW.

5.WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7.CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

8.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.

9.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document Number: 38-05548 Rev. *E

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xPin Configurations CY7C1386DV25 512K XCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitOperation Add. Used Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction RegisterBypass TAP TimingTAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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