Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25 Pin Configurations Ball Fbga Pinout 3 Chip Enable

Page 5

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip Enable)

CY7C1386DV25 (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

A

A

NC

CE

1

BW

C

BW

B

CE

3

BWE

ADSC

ADV

B

NC/144M

A

CE2

CLK

A

NC/576M

BW

D

BW

A

GW

OE

ADSP

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

A

NC

VSS

VDDQ

NC

DQPA

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1387DV25 (1M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

A

1

B

NC

3

A

A

CE

BW

CE

BWE

ADSC

ADV

B

NC/144M

A

CE2

NC

A

CLK

A

NC/576M

BW

GW

OE

ADSP

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

‘VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

A

NC

VSS

VDDQ

NC

NC

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document Number: 38-05548 Rev. *E

Page 5 of 30

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K xCY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDOperation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction RegisterBypass TAP TimingTAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesRead Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change