Cypress CY7C1386DV25, CY7C1387FV25 manual CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

250	CY7C1386DV25-250AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Commercial
	CY7C1387DV25-250AXC

	CY7C1386FV25-250BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1387FV25-250BGC

	CY7C1386FV25-250BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

	CY7C1387FV25-250BGXC

	CY7C1386DV25-250BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1387DV25-250BZC

	CY7C1386DV25-250BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1387DV25-250BZXC

	CY7C1386DV25-250AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Industrial

	CY7C1387DV25-250AXI

	CY7C1386FV25-250BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1387FV25-250BGI

	CY7C1386FV25-250BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

	CY7C1387FV25-250BGXI

	CY7C1386DV25-250BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1387DV25-250BZI

	CY7C1386DV25-250BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1387DV25-250BZXI

Document Number: 38-05548 Rev. *E

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xCY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDOperation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1386DV25/CY7C1386FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1387DV25/CY7C1387FV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Output Load Equivalent TAP AC Switching CharacteristicsTAP AC Test Conditions Parameter Description Min Max Unit ClockIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance PackageParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching CharacteristicsSetup Times Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History