Cypress CY7C1386DV25, CY7C1387DV25, CY7C1387FV25 manual Pin Definitions, Name Description, Bwc, Bwd

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CY7C1386DV25, CY7C1386FV25

Pin Definitions

 

 

 

 

 

CY7C1387DV25, CY7C1387FV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

IO

 

 

Description

 

 

 

 

 

 

 

A0, A1, A

 

 

Input-

Address inputs used to select one of the address locations. Sampled at the

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and

CE

3 [2]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

are sampled active. A1: A0 are fed to the two-bit counter..

 

 

 

 

A,

 

 

 

B

 

 

Input-

Byte write select inputs, active LOW. Qualified with

 

to conduct byte writes

 

BW

BW

 

 

BWE

 

BWC, BWD

Synchronous

to the SRAM. Sampled on the rising edge of CLK.

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Global write enable input, active LOW. When asserted LOW on the rising edge

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

of CLK, a global write is conducted (all bytes are written, regardless of the values

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on BWX and BWE).

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

signal must be asserted LOW to conduct a byte write.

 

 

 

 

 

 

 

CLK

 

 

Input-

Clock input. Used to capture all synchronous inputs to the device. Also used to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

increment the burst counter when ADV is asserted LOW, during a burst operation.

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

Input-

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

if CE1 is HIGH.

CE

1 is sampled only when a new external address is loaded.

 

CE2 [2]

 

 

Input-

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

only when a new external address is loaded.

 

 

 

 

 

 

 

 

 

3 [2]

 

 

Input-

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE1 and CE2 to select or deselect the device. Not connected for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA. Where referenced, CE3 [2] is assumed active throughout this document for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA. CE3 is sampled only when a new external address is loaded.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Output enable, asynchronous input, active LOW. Controls the direction of the

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins are tri-stated, and act as input data pins. OE is masked during the first clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of a read cycle when emerging from a deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Advance input signal, sampled on the rising edge of CLK, active LOW. When

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted, it automatically increments the address in a burst cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from processor, sampled on the rising edge of CLK, active

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

LOW. When asserted LOW, addresses presented to the device are captured in the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address registers. A1: A0 are also loaded into the burst counter. When ADSP and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

deasserted HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from controller, sampled on the rising edge of CLK, active

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

LOW. When asserted LOW, addresses presented to the device are captured in the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address registers. A1: A0 are also loaded into the burst counter. When ADSP and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSC are both asserted, only ADSP is recognized.

 

 

 

 

 

 

 

ZZ

 

 

Input-

ZZ sleep input, active HIGH. When asserted HIGH places the device in a

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

non-time-critical sleep condition with data integrity preserved. For normal operation,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

this pin has to be LOW or left floating. ZZ pin has an internal pull down.

 

 

 

 

 

 

 

DQs, DQPs

 

 

IO-

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in the memory location specified by the addresses presented during the previous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock rise of the read cycle. The direction of the pins is controlled by OE. When OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

placed in a tri-state condition.

 

 

 

 

 

VDD

Power Supply

Power supply inputs to the core of the device.

Document Number: 38-05548 Rev. *E

 

 

 

 

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xPin Configurations CY7C1386DV25 512K XCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitOperation Add. Used Function CY7C1386DV25/CY7C1386FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1387DV25/CY7C1387FV25TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Output Load Equivalent TAP AC Switching CharacteristicsTAP AC Test Conditions Parameter Description Min Max Unit ClockIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance PackageParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching CharacteristicsSetup Times Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History