Cypress CY7C68053 Pin Descriptions, FX2LP18 Pin Descriptions, Name Type Default Description

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CY7C68053

4.1CY7C68053 Pin Descriptions

Table 4-1. FX2LP18 Pin Descriptions [9]

56 VFBGA

Name

Type

Default

Description

2D

AVCC

Power

N/A

Analog VCC. Connect this pin to 3.3V power source. This signal provides

 

 

 

 

power to the analog section of the chip.

 

 

 

 

Appropriate bulk/bypass capacitance should be provided for this

 

 

 

 

supply rail.

1D

AVCC

Power

N/A

Analog VCC. Connect this pin to 3.3V power source. This signal provides

 

 

 

 

power to the analog section of the chip.

2F

AGND

Ground

N/A

Analog Ground. Connect this pin to ground with as short a path as

 

 

 

 

possible.

1F

AGND

Ground

N/A

Analog Ground. Connect to this pin ground with as short a path as

 

 

 

 

possible.

1E

DMINUS

I/O/Z

Z

USB D– Signal. Connect this pin to the USB D– signal.

 

 

 

 

 

2E

DPLUS

I/O/Z

Z

USB D+ Signal. Connect this pin to the USB D+ signal.

8B

RESET#

Input

N/A

Active LOW Reset. This pin resets the entire chip. See Section 3.9 ”Reset

 

 

 

 

and Wakeup” on page 5 for more details.

1C

XTALIN

Input

N/A

Crystal Input. Connect this signal to a 24 MHz parallel resonant, funda-

 

 

 

 

mental mode crystal and load capacitor to GND.

 

 

 

 

It is also correct to drive XTALIN with an external 24-MHz square wave

 

 

 

 

derived from another clock source.

2C

XTALOUT

Output

N/A

Crystal Output. Connect this signal to a 24 MHz parallel resonant, funda-

 

 

 

 

mental mode crystal and load capacitor to GND.

 

 

 

 

If an external clock is used to drive XTALIN, leave this pin open.

2B

CLKOUT

O/Z

12 MHz

CLKOUT. 12-, 24- or 48-MHz clock, phase locked to the 24 MHz input

 

 

 

 

clock. The 8051 defaults to 12 MHz operation. The 8051 may tri-state this

 

 

 

 

output by setting CPUCS.1 = 1.

Port A

 

 

 

 

8G

PA0 or

I/O/Z

I

Multiplexed pin whose function is selected by PORTACFG.0

 

INT0#

 

(PA0)

PA0 is a bidirectional IO port pin.

 

 

 

 

INT0# is the active LOW 8051 INT0 interrupt input signal, which is either

 

 

 

 

edge triggered (IT0 = 1) or level triggered (IT0 = 0).

6G

PA1 or

I/O/Z

I

Multiplexed pin whose function is selected by:

 

INT1#

 

(PA1)

PORTACFG.1

 

 

 

 

PA1 is a bidirectional IO port pin.

 

 

 

 

INT1# is the active LOW 8051 INT1 interrupt input signal, which is either

 

 

 

 

edge triggered (IT1 = 1) or level triggered (IT1 = 0).

8F

PA2 or

I/O/Z

I

Multiplexed pin whose function is selected by two bits:

 

SLOE

 

(PA2)

IFCONFIG[1:0].

 

 

 

 

PA2 is a bidirectional IO port pin.

 

 

 

 

SLOE is an input-only output enable with programmable polarity

 

 

 

 

(FIFOPINPOLAR.4) for the slave FIFO’s connected to FD[7:0] or FD[15:0].

7F

PA3 or

I/O/Z

I

Multiplexed pin whose function is selected by:

 

WU2

 

(PA3)

WAKEUP.7 and OEA.3

 

 

 

 

PA3 is a bidirectional IO port pin.

 

 

 

 

WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit

 

 

 

 

(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in

 

 

 

 

suspend and WU2EN = 1, a transition on this pin starts up the oscillator

 

 

 

 

and interrupts the 8051 to allow it to exit the suspend mode. Asserting this

 

 

 

 

pin inhibits the chip from suspending, if WU2EN = 1.

Note

9.Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby. Note also that no pins should be driven while the device is powered down

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Contents CY7C68053 Features Block DiagramCypress Semiconductor Corporation USB Signaling Speed ApplicationsFunctional Overview 8051 MicroprocessorUSB Boot Methods Bus-powered ApplicationsI2C Bus BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset and Wakeup Reset Timing ValuesCondition Program/Data RAM Register AddressesEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Default High-Speed Alternate Settings3 External Fifo InterfaceGpif Autopointer Access USB Uploads and DownloadsECC Generation6 18 I2C Controller18.2 I2C Interface Boot Load Access 18.3 I2C Interface General Purpose AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Name Type Default Description CY7C68053 Pin DescriptionsFX2LP18 Pin Descriptions Port aFIFOADR0 FIFOADR1Pktend SLCS#Slrd IFCONFIG10 Slwr IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC1B2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16ECC2B0 ECC2B1Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0 EpieEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneEP1OUTCS Busy StallEP1INCS EP2CSE6CF TC9 TC8TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELAutoptrsetup DPL0DPH0 SELRCAP2L RCAP2HTL2 TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics AC Electrical Characteristics Gpif Synchronous SignalsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSequence Diagram Single and Burst Synchronous Read ExampleIfclk Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Package Diagram Ordering InformationDevelopment Tool Kit PCB Layout Recommendations Issue Date Orig. Description of Change Document HistoryOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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