Cypress CY7C68053 manual Slrd IFCONFIG10, Slwr IFCONFIG10, Flaga IFCONFIG10, Flagb IFCONFIG10

Page 14

 

 

 

 

 

CY7C68053

 

 

 

 

 

 

Table 4-1. FX2LP18 Pin Descriptions (continued)[9]

56 VFBGA

Name

 

Type

Default

Description

PORT D

 

 

 

 

 

8A

PD0 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[8]

 

 

(PD0)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[8] is the bidirectional FIFO/GPIF data bus.

7A

PD1 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[9]

 

 

(PD1)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[9] is the bidirectional FIFO/GPIF data bus.

6B

PD2 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[10]

 

 

(PD2)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[10] is the bidirectional FIFO/GPIF data bus.

6A

PD3 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[11]

 

 

(PD3)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[11] is the bidirectional FIFO/GPIF data bus.

3B

PD4 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[12]

 

 

(PD4)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[12] is the bidirectional FIFO/GPIF data bus.

3A

PD5 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[13]

 

 

(PD5)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[13] is the bidirectional FIFO/GPIF data bus.

3C

PD6 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[14]

 

 

(PD6)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[14] is the bidirectional FIFO/GPIF data bus.

2A

PD7 or

 

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FD[15]

 

 

(PD7)

EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

FD[15] is the bidirectional FIFO/GPIF data bus.

 

 

 

 

 

 

1A

RDY0 or

 

Input

N/A

Multiplexed pin whose function is selected by the following bits:

 

SLRD

 

 

 

IFCONFIG[1:0].

 

 

 

 

 

RDY0 is a GPIF input signal.

 

 

 

 

 

SLRD is the input only read strobe with programmable polarity (FIFOPIN-

 

 

 

 

 

POLAR.3) for the slave FIFO’s connected to FD[7:0] or FD[15:0].

1B

RDY1 or

 

Input

N/A

Multiplexed pin whose function is selected by the following bits:

 

SLWR

 

 

 

IFCONFIG[1:0].

 

 

 

 

 

RDY1 is a GPIF input signal.

 

 

 

 

 

SLWR is the input only write strobe with programmable polarity (FIFOPIN-

 

 

 

 

 

POLAR.2) for the slave FIFO’s connected to FD[7:0] or FD[15:0].

7H

CTL0 or

 

O/Z

H

Multiplexed pin whose function is selected by the following bits:

 

FLAGA

 

 

 

IFCONFIG[1:0].

 

 

 

 

 

CTL0 is a GPIF control output.

 

 

 

 

 

FLAGA is a programmable slave FIFO output status flag signal.

 

 

 

 

 

Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.

7G

CTL1 or

 

O/Z

H

Multiplexed pin whose function is selected by the following bits:

 

FLAGB

 

 

 

IFCONFIG[1:0].

 

 

 

 

 

CTL1 is a GPIF control output.

 

 

 

 

 

FLAGB is a programmable slave FIFO output status flag signal.

 

 

 

 

 

Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.

8H

CTL2 or

 

O/Z

H

Multiplexed pin whose function is selected by the following bits:

 

FLAGC

 

 

 

IFCONFIG[1:0].

 

 

 

 

 

CTL2 is a GPIF control output.

 

 

 

 

 

FLAGC is a programmable slave FIFO output status flag signal.

 

 

 

 

 

Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.

Document # 001-06120 Rev *F

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Contents Cypress Semiconductor Corporation CY7C68053 FeaturesBlock Diagram Functional Overview USB Signaling SpeedApplications 8051 MicroprocessorI2C Bus USB Boot MethodsBus-powered Applications BusesINT2 USB Interrupts Priority INT2VEC Value SourceCondition Reset and WakeupReset Timing Values Endpoint RAM Program/Data RAMRegister Addresses Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Gpif Default High-Speed Alternate Settings3External Fifo Interface ECC Generation6 Autopointer AccessUSB Uploads and Downloads 18 I2C ControllerPin Assignments 18.2 I2C Interface Boot Load Access18.3 I2C Interface General Purpose Access CY7C68053 56-pin Vfbga Pin Assignment Top view FX2LP18 Pin Descriptions Name Type Default DescriptionCY7C68053 Pin Descriptions Port aPktend FIFOADR0FIFOADR1 SLCS#Flaga IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC2B0 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B1EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie Gpifwf GpifdoneEP1INCS EP1OUTCSBusy Stall EP2CSTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 E6CFTC9 TC8 EP2GPIFFLGSELDPH0 AutoptrsetupDPL0 SELTL2 RCAP2LRCAP2H TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics USB Transceiver AC Electrical CharacteristicsGpif Synchronous Signals Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressIfclk Sequence DiagramSingle and Burst Synchronous Read Example Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Development Tool Kit Package DiagramOrdering Information PCB Layout Recommendations OSG Issue Date Orig. Description of ChangeDocument History ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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