Cypress CY7C68053 manual Default Full-Speed Alternate Settings3

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CY7C68053

vertical columns of Figure 3-5. When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example, in high-speed the maximum packet size is 512 bytes, but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer, in full-speed only the first

64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configu- ration is:

EP2–1024 double buffered; EP6–512 quad buffered (column 8).

Figure 3-5. Endpoint Configuration

EP0 IN&OUT

64

64

64

64

64

64

64

64

64

64

64

64

EP1 IN

64

64

64

64

64

64

64

64

64

64

64

64

EP1 OUT

64

64

64

64

64

64

64

64

64

64

64

64

 

EP2

EP2

EP2

EP2

EP2

EP2

EP2

EP2

EP2

EP2

EP2

EP2

 

512

512

512

512

512

512

1024

1024

1024

512

 

 

 

 

 

 

 

512

512

512

512

512

512

512

1024

 

 

 

 

 

1024

 

 

 

 

 

 

EP4

EP4

EP4

 

 

 

 

 

 

512

 

 

 

 

 

 

 

 

 

 

 

 

 

512

512

512

512

512

512

1024

1024

1024

EP6

1024

1024

 

512

512

512

512

512

512

 

 

 

512

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EP6

EP6

EP6

EP6

EP6

EP6

EP6

EP6

EP6

512

1024

 

 

512

512

 

512

512

 

512

512

 

 

1024

 

1024

1024

1024

512

1024

 

512

512

512

512

512

512

 

 

 

 

 

 

EP8

EP8

 

 

EP8

 

 

EP8

 

 

EP8

 

 

1024

 

512

512

1024

512

512

1024

512

512

1024

512

512

 

512

512

 

 

512

512

 

512

512

 

512

512

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

12

3.12.5Default Full-Speed Alternate Settings

Table 3-4. Default Full-Speed Alternate Settings[3, 4]

Alternate Setting

0

1

2

3

ep0

64

64

64

64

 

 

 

 

 

ep1out

0

64 bulk

64 int

64 int

 

 

 

 

 

ep1in

0

64 bulk

64 int

64 int

 

 

 

 

 

ep2

0

64 bulk out (2×)

64 int out (2×)

64 iso out (2×)

 

 

 

 

 

ep4

0

64 bulk out (2×)

64 bulk out (2×)

64 bulk out (2×)

 

 

 

 

 

ep6

0

64 bulk in (2×)

64 int in (2×)

64 iso in (2×)

 

 

 

 

 

ep8

0

64 bulk in (2×)

64 bulk in (2×)

64 bulk in (2×)

 

 

 

 

 

Notes

3.‘0’ means ‘not implemented.’

4.‘2×’ means ‘double buffered.’

Document # 001-06120 Rev *F

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Contents Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation 8051 Microprocessor USB Signaling SpeedApplications Functional OverviewBuses USB Boot MethodsBus-powered Applications I2C BusPriority INT2VEC Value Source INT2 USB InterruptsReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsExternal Fifo Interface Default High-Speed Alternate Settings3Gpif 18 I2C Controller Autopointer AccessUSB Uploads and Downloads ECC Generation618.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Port a Name Type Default DescriptionCY7C68053 Pin Descriptions FX2LP18 Pin DescriptionsSLCS# FIFOADR0FIFOADR1 PktendFlagb IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flaga IFCONFIG10Ground FX2LP18 Register Summary Register SummaryECC2B1 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B0Gpifwf Gpifdone Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0INEP2CS EP1OUTCSBusy Stall EP1INCSEP2GPIFFLGSEL E6CFTC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0SEL AutoptrsetupDPL0 DPH0TH2 RCAP2LRCAP2H TL2Operating Conditions Absolute Maximum RatingsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSloe Slrd Sequence DiagramSingle and Burst Synchronous Read Example IfclkSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations ARI Issue Date Orig. Description of ChangeDocument History OSG

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.