Cypress CY7C68053 manual INT2 USB Interrupts, Priority INT2VEC Value Source

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CY7C68053

pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ‘jump’ instruction to the USB interrupt service routine.

The FX2LP18 jump instruction is encoded as shown in Table 3-2.

Table 3-2. INT2 USB Interrupts

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2VEC byte. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page.

USB INTERRUPT TABLE FOR INT2

Priority

INT2VEC Value

Source

Notes

1

00

SUDAV

Set-up Data Available

 

 

 

 

2

04

SOF

Start of Frame (or microframe)

 

 

 

 

3

08

SUTOK

Set-up Token Received

 

 

 

 

4

0C

SUSPEND

USB Suspend request

 

 

 

 

5

10

USB RESET

Bus reset

 

 

 

 

6

14

HISPEED

Entered high-speed operation

 

 

 

 

7

18

EP0ACK

FX2LP18 ACK’d the CONTROL Handshake

 

 

 

 

8

1C

 

Reserved

 

 

 

 

9

20

EP0-IN

EP0-IN ready to be loaded with data

 

 

 

 

10

24

EP0-OUT

EP0-OUT has USB data

 

 

 

 

11

28

EP1-IN

EP1-IN ready to be loaded with data

 

 

 

 

12

2C

EP1-OUT

EP1-OUT has USB data

 

 

 

 

13

30

EP2

IN: buffer available. OUT: buffer has data

 

 

 

 

14

34

EP4

IN: buffer available. OUT: buffer has data

 

 

 

 

15

38

EP6

IN: buffer available. OUT: buffer has data

 

 

 

 

16

3C

EP8

IN: buffer available. OUT: buffer has data

 

 

 

 

17

40

IBN

IN-Bulk-NAK (any IN endpoint)

 

 

 

 

18

44

 

Reserved

 

 

 

 

19

48

EP0PING

EP0 OUT was Pinged and it NAK’d

 

 

 

 

20

4C

EP1PING

EP1 OUT was Pinged and it NAK’d

 

 

 

 

21

50

EP2PING

EP2 OUT was Pinged and it NAK’d

 

 

 

 

22

54

EP4PING

EP4 OUT was Pinged and it NAK’d

 

 

 

 

23

58

EP6PING

EP6 OUT was Pinged and it NAK’d

 

 

 

 

24

5C

EP8PING

EP8 OUT was Pinged and it NAK’d

 

 

 

 

25

60

ERRLIMIT

Bus errors exceeded the programmed limit

 

 

 

 

26

64

 

 

 

 

 

 

27

68

 

Reserved

 

 

 

 

28

6C

 

Reserved

 

 

 

 

29

70

EP2ISOERR

ISO EP2 OUT PID sequence error

 

 

 

 

30

74

EP4ISOERR

ISO EP4 OUT PID sequence error

 

 

 

 

31

78

EP6ISOERR

ISO EP6 OUT PID sequence error

 

 

 

 

32

7C

EP8ISOERR

ISO EP8 OUT PID sequence error

 

 

 

 

Document # 001-06120 Rev *F

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Contents Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation USB Signaling Speed ApplicationsFunctional Overview 8051 MicroprocessorUSB Boot Methods Bus-powered ApplicationsI2C Bus BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3External Fifo Interface Default High-Speed Alternate Settings3Gpif Autopointer Access USB Uploads and DownloadsECC Generation6 18 I2C Controller18.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Name Type Default Description CY7C68053 Pin DescriptionsFX2LP18 Pin Descriptions Port aFIFOADR0 FIFOADR1Pktend SLCS#Slrd IFCONFIG10 Slwr IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC1B2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16ECC2B0 ECC2B1Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0 EpieEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneEP1OUTCS Busy StallEP1INCS EP2CSE6CF TC9 TC8TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELAutoptrsetup DPL0DPH0 SELRCAP2L RCAP2HTL2 TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSequence Diagram Single and Burst Synchronous Read ExampleIfclk Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations Issue Date Orig. Description of Change Document HistoryOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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