Cypress CY7C68053 manual Sequence Diagram of a Single and Burst Asynchronous Write

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CY7C68053

9.13.4Sequence Diagram of a Single and Burst Asynchronous Write

Figure 9-18. Slave FIFO Asynchronous Write Sequence and Timing Diagram[17]

 

tSFA

 

tFAH

tSFA

 

 

 

 

 

 

 

 

tFAH

FIFOADR

 

 

 

 

 

 

 

 

 

 

 

 

 

t=0

tWRpwl

tWRpwh

T=0

tWRpwl

tWRpwh

 

tWRpwl

tWRpwh

tWRpwl

 

tWRpwh

 

 

 

 

 

 

 

 

 

 

SLWR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t =1

t=3

T=1

T=3

T=4

T=6

T=7

T=9

 

SLCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tXFLG

 

 

 

 

 

 

 

 

 

tXFLG

 

 

 

 

 

 

 

 

 

 

 

 

 

FLAGS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSFD

tFDH

 

tSFD

tFDH

 

tSFD

tFDH

tSFD

tFDH

 

DATA

 

 

N

 

 

N+1

 

 

N+2

 

 

N+3

 

 

 

t=2

 

 

T=2

 

 

T=5

 

T=8

 

tPEpwl

tPEpwh

 

 

 

 

 

 

 

 

 

 

 

 

PKTEND

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 9-18illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND.

•At t = 0 the FIFO address is applied, ensuring that it meets the set-up time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications).

•At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

•At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR.

•At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then the FIFO pointer is

incremented. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR.

The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented.

In Figure 9-18once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device must be designed to not assert SLWR and the PKTEND signal at the same time. It must be designed to assert the PKTEND after SLWR is deasserted and meet the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion.

Document # 001-06120 Rev *F

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Contents CY7C68053 Features Block DiagramCypress Semiconductor Corporation USB Signaling Speed ApplicationsFunctional Overview 8051 MicroprocessorUSB Boot Methods Bus-powered ApplicationsI2C Bus BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset and Wakeup Reset Timing ValuesCondition Program/Data RAM Register AddressesEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Default High-Speed Alternate Settings3 External Fifo InterfaceGpif Autopointer Access USB Uploads and DownloadsECC Generation6 18 I2C Controller18.2 I2C Interface Boot Load Access 18.3 I2C Interface General Purpose AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Name Type Default Description CY7C68053 Pin DescriptionsFX2LP18 Pin Descriptions Port aFIFOADR0 FIFOADR1Pktend SLCS#Slrd IFCONFIG10 Slwr IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC1B2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16ECC2B0 ECC2B1Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0 EpieEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneEP1OUTCS Busy StallEP1INCS EP2CSE6CF TC9 TC8TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELAutoptrsetup DPL0DPH0 SELRCAP2L RCAP2HTL2 TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics AC Electrical Characteristics Gpif Synchronous SignalsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSequence Diagram Single and Burst Synchronous Read ExampleIfclk Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Package Diagram Ordering InformationDevelopment Tool Kit PCB Layout Recommendations Issue Date Orig. Description of Change Document HistoryOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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