Cypress CY7C68053 manual Applications, Functional Overview, USB Signaling Speed, Microprocessor

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CY7C68053

Cypress Semiconductor Corporation’s MoBL-USBFX2LP18 (CY7C68053) is a low-voltage (1.8 volt) version of the EZ- USB® FX2LP (CY7C68013A), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.

The ingenious architecture of MoBL-USB FX2LP18 results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low- cost 8051 microcontroller in a package as small as a 56 VFBGA (5 mm x 5 mm). Because it incorporates the USB 2.0 transceiver, the MoBL-USB FX2LP18 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With MoBL-USB FX2LP18, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcon- troller for application-specific functions and decreasing devel- opment time to ensure USB compatibility.

The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.

The 56VFBGA package is defined for the family.

The MoBL-USB FX2LP18 is also referred to as FX2LP18 in this document.

2.0Applications

There are a wide variety of applications for the MoBL-USB FX2LP18. It is used in cell phone, smart phones, PDAs, and MP3 players, to name a few.

The ‘Reference Designs’ section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. For more infor- mation, visit http://www.cypress.com.

3.0Functional Overview

The functionality of this chip is described in the sections below.

3.1USB Signaling Speed

FX2LP18 operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000.

•Full-speed, with a signaling bit rate of 12 Mbps

•High-speed, with a signaling bit rate of 480 Mbps.

FX2LP18 does not support the low-speed signaling mode of 1.5 Mbps.

3.28051 Microprocessor

The 8051 microprocessor embedded in the FX2LP18 family has 256 bytes of register RAM, an expanded interrupt system, and three timer/counters.

3.2.18051 Clock Frequency

FX2LP18 has an on-chip oscillator circuit that uses an external

24 MHz (±100-ppm) crystal with the following characteristics:

•Parallel resonant

•Fundamental mode

•500 µW drive level

•12 pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynami- cally.

Figure 3-1. Crystal Configuration

C1 24 MHz C2

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

pf

 

 

 

12

 

pf

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 × PLL

12 pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency — 48, 24, or 12 MHz.

3.2.2Special Function Registers

Certain 8051 Special Function Register (SFR) addresses are populated to provide fast access to critical FX2LP18 functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with ‘0’ and ‘8’ contain bit-addressable registers. The four IO ports A – D use the SFR addresses used in the standard 8051 for ports 0 – 3, which are not implemented in FX2LP18. Because of the faster and more efficient SFR addressing, the FX2LP18 IO ports are not addressable in external RAM space (using the MOVX instruction).

Document # 001-06120 Rev *F

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Contents Cypress Semiconductor Corporation CY7C68053 FeaturesBlock Diagram Functional Overview USB Signaling SpeedApplications 8051 MicroprocessorI2C Bus USB Boot MethodsBus-powered Applications BusesINT2 USB Interrupts Priority INT2VEC Value SourceCondition Reset and WakeupReset Timing Values Endpoint RAM Program/Data RAMRegister Addresses Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Gpif Default High-Speed Alternate Settings3External Fifo Interface ECC Generation6 Autopointer AccessUSB Uploads and Downloads 18 I2C ControllerPin Assignments 18.2 I2C Interface Boot Load Access18.3 I2C Interface General Purpose Access CY7C68053 56-pin Vfbga Pin Assignment Top view FX2LP18 Pin Descriptions Name Type Default DescriptionCY7C68053 Pin Descriptions Port aPktend FIFOADR0FIFOADR1 SLCS#Flaga IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC2B0 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B1EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie Gpifwf GpifdoneEP1INCS EP1OUTCSBusy Stall EP2CSTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 E6CFTC9 TC8 EP2GPIFFLGSELDPH0 AutoptrsetupDPL0 SELTL2 RCAP2LRCAP2H TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics USB Transceiver AC Electrical CharacteristicsGpif Synchronous Signals Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressIfclk Sequence DiagramSingle and Burst Synchronous Read Example Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Development Tool Kit Package DiagramOrdering Information PCB Layout Recommendations OSG Issue Date Orig. Description of ChangeDocument History ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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