Cypress CY7C68053 manual Document History, Issue Date Orig. Description of Change, Osg, Ari

Page 39

CY7C68053

Document History Page

Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller

Document Number: 001-06120

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

430449

03/03/06

OSG

New data sheet

 

 

 

 

 

*A

434754

03/24/06

OSG

In Section 3.3, stated that SCL and SDA pins can be connected to VCC or

 

 

 

 

VCC_IO

 

 

 

 

Changed sections 3.5, 3.18.1 and pin descriptions of SCL, SDA to indicate that

 

 

 

 

since DISCON=1 after reset, an EEPROM or EEPROM emulation is required

 

 

 

 

on the I2C interface

 

 

 

 

In pin description table, renamed pin 2H (Reserved) to Ground

 

 

 

 

In Section 6, added statement “The GPIO’s are not over voltage tolerant,

 

 

 

 

except the SCL and SDA pins, which are 3.3V tolerant“

 

 

 

 

In Section 8,added a footnote to the DC char table stating that AVcc can be

 

 

 

 

floated in low power mode

 

 

 

 

In Section 8, changed VIHmax in DC char table from 3.6V to VCC_IO + 10%

*B

465471

See ECN

OSG

Changed the recommendation for the pull up resistors on I2C

 

 

 

 

Split Icc into 4 different values, corresponding to the different voltage supplies

 

 

 

 

Changed Isus typical to 20uA and 220uA

 

 

 

 

Added section 3.9.3 on suspend current considerations

*C

484726

See ECN

ARI

Removed all references the part number CY7C68055. Corrected the bullet in

 

 

 

 

Features to state that 24 GPIO’s are available. Added the Test ID (TID#) to the

 

 

 

 

Features on the front page. Made changes to the block diagram on the first

 

 

 

 

page (this is now a Visio drawing instead of a Framemaker drawing). Corrected

 

 

 

 

the Ambient Temperature with Power Supplied. Moved figure titles to meet the

 

 

 

 

new template. Checked grammar. Took out 9-bit address bus from the block

 

 

 

 

diagram on the first page. Corrected Figure 4.1

*D

492009

See ECN

OSG

Added Icc data in DC Characteristics and Maximum Power dissipation

 

 

 

 

 

*E

500408

See ECN

OSG

Changed ESD spec to 1500V

 

 

 

 

 

*F

502115

See ECN

OSG

Changed ESD spec to 2000V and 1500V only for SCL and SDA pins.

 

 

 

 

Added min spec for tOEoff

 

 

 

 

Changed Icc and power dissipation numbers

Document # 001-06120 Rev *F

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Contents CY7C68053 Features Block DiagramCypress Semiconductor Corporation 8051 Microprocessor USB Signaling SpeedApplications Functional OverviewBuses USB Boot MethodsBus-powered Applications I2C BusPriority INT2VEC Value Source INT2 USB InterruptsReset and Wakeup Reset Timing ValuesCondition Program/Data RAM Register AddressesEndpoint RAM Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsDefault High-Speed Alternate Settings3 External Fifo InterfaceGpif 18 I2C Controller Autopointer AccessUSB Uploads and Downloads ECC Generation618.2 I2C Interface Boot Load Access 18.3 I2C Interface General Purpose AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Port a Name Type Default DescriptionCY7C68053 Pin Descriptions FX2LP18 Pin DescriptionsSLCS# FIFOADR0FIFOADR1 PktendFlagb IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flaga IFCONFIG10Ground FX2LP18 Register Summary Register SummaryECC2B1 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B0Gpifwf Gpifdone Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0INEP2CS EP1OUTCSBusy Stall EP1INCSEP2GPIFFLGSEL E6CFTC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0SEL AutoptrsetupDPL0 DPH0TH2 RCAP2LRCAP2H TL2Operating Conditions Absolute Maximum RatingsDC Characteristics AC Electrical Characteristics Gpif Synchronous SignalsUSB Transceiver Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSloe Slrd Sequence DiagramSingle and Burst Synchronous Read Example IfclkSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Package Diagram Ordering InformationDevelopment Tool Kit PCB Layout Recommendations ARI Issue Date Orig. Description of ChangeDocument History OSG

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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