Cypress CY7C68053 I2C Bus, Buses, USB Boot Methods, Bus-powered Applications, Interrupt System

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CY7C68053

Table 3-1. Special Function Registers

x

8x

9x

Ax

Bx

Cx

Dx

Ex

Fx

 

 

 

 

 

 

 

 

 

0

IOA

IOB

IOC

IOD

SCON1

PSW

ACC

B

1

SP

EXIF

INT2CLR

IOE

SBUF1

 

 

 

2

DPL0

MPAGE

 

OEA

 

 

 

 

3

DPH0

 

 

OEB

 

 

 

 

4

DPL1

 

 

OEC

 

 

 

 

5

DPH1

 

 

OED

 

 

 

 

6

DPS

 

 

OEE

 

 

 

 

7

PCON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

TCON

SCON0

IE

IP

T2CON

EICON

EIE

EIP

9

TMOD

SBUF0

 

 

 

 

 

 

A

TL0

AUTOPTRH1

EP2468STAT

EP01STAT

RCAP2L

 

 

 

B

TL1

AUTOPTRL1

EP24FIFOFLGS

GPIFTRIG

RCAP2H

 

 

 

C

TH0

Reserved

EP68FIFOFLGS

 

TL2

 

 

 

D

TH1

AUTOPTRH2

 

GPIFSGLDATH

TH2

 

 

 

E

CKCON

AUTOPTRL2

 

GPIFSGLDATLX

 

 

 

 

F

 

Reserved

AUTOPTRSET-UP

GPIFSGLDATLNOX

 

 

 

 

3.3I2C™ Bus

FX2LP18 supports the I2C bus as a master only at 100-/400- KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to either VCC or VCC_IO, even if no I2C device is connected.(Connecting to VCC_IO may be more convenient.)

3.4Buses

This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on IO ports B and D.

plugged in, with no hint that the initial download step has occurred.

Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1, the firmware does.

3.5USB Boot Methods

During the power-up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is 0xC2. If found, it boot-loads the EEPROM contents into internal RAM (0xC2 load). If no EEPROM is present, an external processor must emulate an I2C slave. The FX2LP18 does not enumerate using internally stored descriptors (for example, Cypress’ VID/PID/DID is not used for enumer- ation).[1]

3.7Bus-powered Applications

The FX2LP18 fully supports bus-powered designs by enumer- ating with less than 100 mA as required by the USB 2.0 speci- fication.

3.8Interrupt System

The FX2LP18 interrupts are described in this section.

3.8.1INT2 Interrupt Request and Enable Registers

3.6ReNumeration™

Because the FX2LP18’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.

When first plugged into USB, the FX2LP18 enumerates automatically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP18 enumerates again, this time as a device defined by the downloaded infor- mation. This patented two-step process, called ReNumeration, happens instantly when the device is

Note

FX2LP18 implements an autovector feature for INT2. There are 27 INT2 (USB) vectors. See the MoBL-USB™ Technical Reference Manual (TRM) for more details.

3.8.2USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is normally required to identify the individual USB interrupt source, the FX2LP18 provides a second level of interrupt vectoring, called ‘Autovec- toring.’ When a USB interrupt is asserted, the FX2LP18

1.The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

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Contents CY7C68053 Features Block DiagramCypress Semiconductor Corporation 8051 Microprocessor USB Signaling SpeedApplications Functional OverviewBuses USB Boot MethodsBus-powered Applications I2C BusPriority INT2VEC Value Source INT2 USB InterruptsReset and Wakeup Reset Timing ValuesCondition Program/Data RAM Register AddressesEndpoint RAM Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsDefault High-Speed Alternate Settings3 External Fifo InterfaceGpif 18 I2C Controller Autopointer AccessUSB Uploads and Downloads ECC Generation618.2 I2C Interface Boot Load Access 18.3 I2C Interface General Purpose AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Port a Name Type Default DescriptionCY7C68053 Pin Descriptions FX2LP18 Pin DescriptionsSLCS# FIFOADR0FIFOADR1 PktendFlagb IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flaga IFCONFIG10Ground FX2LP18 Register Summary Register SummaryECC2B1 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B0Gpifwf Gpifdone Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0INEP2CS EP1OUTCSBusy Stall EP1INCSEP2GPIFFLGSEL E6CFTC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0SEL AutoptrsetupDPL0 DPH0TH2 RCAP2LRCAP2H TL2Operating Conditions Absolute Maximum RatingsDC Characteristics AC Electrical Characteristics Gpif Synchronous SignalsUSB Transceiver Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSloe Slrd Sequence DiagramSingle and Burst Synchronous Read Example IfclkSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Package Diagram Ordering InformationDevelopment Tool Kit PCB Layout Recommendations ARI Issue Date Orig. Description of ChangeDocument History OSG

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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