Cypress CY7C68053 manual FX2LP18 Register Summary

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CY7C68053

5.0Register Summary

FX2LP18 register bit definitions are described in the MoBL-USB TRM in greater detail.

Table 5-1. FX2LP18 Register Summary

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

 

 

GPIF Waveform Memories

 

 

 

 

 

 

 

 

 

 

E400

128

WAVEDATA

GPIF Waveform

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

Descriptor 0, 1, 2, 3 data

 

 

 

 

 

 

 

 

 

 

E480

128

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL CONFIGURATION

 

 

 

 

 

 

 

 

 

 

E50D

 

GPCR2

General Purpose Configu-

Reserved

Reserved

Reserved

FULL_SPEE

Reserved

Reserved

Reserved

Reserved

00000000

R

 

 

 

ration Register 2

 

 

 

D_ONLY

 

 

 

 

 

 

E600

1

CPUCS

CPU Control & Status

0

0

PORTCSTB

CLKSPD1

CLKSPD0

CLKINV

CLKOE

8051RES

00000010

rrbbbbbr

E601

1

IFCONFIG

Interface Configuration

IFCLKSRC

3048MHZ

IFCLKOE

IFCLKPOL

ASYNC

GSTATE

IFCFG1

IFCFG0

10000000

RW

 

 

 

(Ports, GPIF, slave

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO’s)

 

 

 

 

 

 

 

 

 

 

E602

1

PINFLAGSAB[10]

Slave FIFO FLAGA and

FLAGB3

FLAGB2

FLAGB1

FLAGB0

FLAGA3

FLAGA2

FLAGA1

FLAGA0

00000000

RW

 

 

 

FLAGB Pin Configuration

 

 

 

 

 

 

 

 

 

 

E603

1

PINFLAGSCD[10]

Slave FIFO FLAGC and

FLAGD3

FLAGD2

FLAGD1

FLAGD0

FLAGC3

FLAGC2

FLAGC1

FLAGC0

00000000

RW

 

 

 

FLAGD Pin Configuration

 

 

 

 

 

 

 

 

 

 

E604

1

FIFORESET[10]

Restore FIFO’s to default

NAKALL

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

 

state

 

 

 

 

 

 

 

 

 

 

E605

1

BREAKPT

Breakpoint Control

0

0

0

0

BREAK

BPPULSE

BPEN

0

00000000

rrrrbbbr

E606

1

BPADDRH

Breakpoint Address H

A15

A14

A13

A12

A11

A10

A9

A8

xxxxxxxx

RW

E607

1

BPADDRL

Breakpoint Address L

A7

A6

A5

A4

A3

A2

A1

A0

xxxxxxxx

RW

E608

1

Reserved

Reserved

0

0

0

0

0

0

0

0

00000000

rrrrrrbb

E609

1

FIFOPINPOLAR[10]

Slave FIFO Interface pins

0

0

PKTEND

SLOE

SLRD

SLWR

EF

FF

00000000

rrbbbbbb

 

 

 

polarity

 

 

 

 

 

 

 

 

 

 

E60A

1

REVID

Chip Revision

rv7

rv6

rv5

rv4

rv3

rv2

rv1

rv0

RevA

R

 

 

 

 

 

 

 

 

 

 

 

 

00000001

 

E60B

1

REVCTL[10]

Chip Revision Control

0

0

0

0

0

0

dyn_out

enh_pkt

00000000

rrrrrrbb

 

 

UDMA

 

 

 

 

 

 

 

 

 

 

 

E60C

1

GPIFHOLDAMOUNT

MSTB Hold Time

0

0

0

0

0

0

HOLDTIME1

HOLDTIME0

00000000

rrrrrrbb

 

 

 

(for UDMA)

 

 

 

 

 

 

 

 

 

 

 

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

ENDPOINT CONFIGURATION

 

 

 

 

 

 

 

 

 

 

E610

1

EP1OUTCFG

Endpoint 1-OUT

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

E611

1

EP1INCFG

Endpoint 1-IN

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

E612

1

EP2CFG

Endpoint 2 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

10100010

bbbbbrbb

E613

1

EP4CFG

Endpoint 4 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

10100000

bbbbrrrr

E614

1

EP6CFG

Endpoint 6 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

11100010

bbbbbrbb

E615

1

EP8CFG

Endpoint 8 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

11100000

bbbbrrrr

 

2

Reserved

 

 

 

 

 

 

 

 

 

 

 

E618

1

EP2FIFOCFG[10]

Endpoint 2/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E619

1

EP4FIFOCFG[10]

Endpoint 4/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61A

1

EP6FIFOCFG[10]

Endpoint 6/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61B

1

EP8FIFOCFG[10]

Endpoint 8/slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61C

4

Reserved

 

 

 

 

 

 

 

 

 

 

 

E620

1

EP2AUTOINLENH[10

Endpoint 2 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

 

 

 

Packet Length H

 

 

 

 

 

 

 

 

 

 

E621

1

EP2AUTOINLENL[10]

Endpoint 2 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E622

1

EP4AUTOINLENH[10

Endpoint 4 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

 

 

]

Packet Length H

 

 

 

 

 

 

 

 

 

 

E623

1

EP4AUTOINLENL[10]

Endpoint 4 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E624

1

EP6AUTOINLENH[10

Endpoint 6 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

 

 

]

Packet Length H

 

 

 

 

 

 

 

 

 

 

E625

1

EP6AUTOINLENL[10]

Endpoint 6 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E626

1

EP8AUTOINLENH[10

Endpoint 8 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

 

 

]

Packet Length H

 

 

 

 

 

 

 

 

 

 

E627

1

EP8AUTOINLENL[10]

Endpoint 8 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E628

1

ECCCFG

ECC Configuration

0

0

0

0

0

0

0

ECCM

00000000

rrrrrrrb

E629

1

ECCRESET

ECC Reset

x

x

x

x

x

x

x

x

00000000

W

E62A

1

ECC1B0

ECC1 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62B

1

ECC1B1

ECC1 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

Note

 

 

 

 

 

 

 

 

 

 

 

 

 

10. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for ‘Synchronization Delay.’

 

 

Document # 001-06120 Rev *F

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Contents Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation USB Signaling Speed ApplicationsFunctional Overview 8051 MicroprocessorUSB Boot Methods Bus-powered ApplicationsI2C Bus BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3External Fifo Interface Default High-Speed Alternate Settings3Gpif Autopointer Access USB Uploads and DownloadsECC Generation6 18 I2C Controller18.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view Name Type Default Description CY7C68053 Pin DescriptionsFX2LP18 Pin Descriptions Port aFIFOADR0 FIFOADR1Pktend SLCS#Slrd IFCONFIG10 Slwr IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC1B2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16ECC2B0 ECC2B1Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0 EpieEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneEP1OUTCS Busy StallEP1INCS EP2CSE6CF TC9 TC8TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELAutoptrsetup DPL0DPH0 SELRCAP2L RCAP2HTL2 TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSequence Diagram Single and Burst Synchronous Read ExampleIfclk Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations Issue Date Orig. Description of Change Document HistoryOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.