Cypress CY7C68053 manual Sequence Diagram of a Single and Burst Asynchronous Read

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CY7C68053

9.13.3Sequence Diagram of a Single and Burst Asynchronous Read

Figure 9-16. Slave FIFO Asynchronous Read Sequence and Timing Diagram[17]

 

 

 

 

 

 

t

SFA

 

t

 

 

 

 

t

SFA

 

 

 

 

 

 

 

 

 

tFAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFOADR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t=0

 

 

 

tRDpwl

 

tRDpwh

 

 

 

 

 

 

 

 

tRDpwl

 

tRDpwh

 

tRDpwl

 

tRDpwh

 

tRDpwl tRDpwh

 

 

 

 

 

 

 

 

 

 

 

 

T=0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLRD

t=2

t=3

T=2

T=3

T=4

T=5

T=6

SLCS

 

 

 

 

 

 

 

 

 

 

 

 

tXFLG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tXFLG

 

 

 

 

FLAGS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tXFD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tXFD

 

tXFD

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XFD

 

 

 

 

 

 

DATA

 

 

 

Data (X)

 

N

 

 

 

N

 

 

 

N+1

 

N+2

 

 

N+3

 

 

 

 

 

 

 

 

Driven

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

 

 

t

OEoff

 

tOEon

 

 

 

 

 

 

 

 

 

 

 

 

tOEoff

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OEon

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLOE

t=1

t=4

T=1

T=7

Figure 9-17. Slave FIFO Asynchronous Read Sequence of Events Diagram

FIFO POINTER

SLOE

SLRD

 

SLRD

 

 

SLOE

 

SLOE

SLRD

 

SLRD

SLRD

SLRD

 

 

 

SLOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

N

 

 

N

 

 

 

 

N+1

 

 

 

N+1

 

 

 

N+1

 

 

 

N+1

 

 

N+2

 

 

N+2

 

 

N+3

 

 

 

 

 

 

N+3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO DATA BUS

Not Driven

 

 

Driven: X

 

 

N

 

 

 

 

 

 

N Not Driven N N+1 N+1 N+2 N+2 Not Driven

Figure 9-16illustrates the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read.

•At t = 0, the FIFO address is stable and the SLCS signal is asserted.

•At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data; it is data that was in the FIFO from a prior read cycle.

•At t = 2, SLRD is asserted. The SLRD must meet the min- imum active pulse of tRDpwl and minimum de-active pulse width of tRDpwh. If SLCS is used then, SLCS must be as- serted with SLRD or before SLRD is asserted (for example, the SLCS and SLRD signals must both be asserted to start a valid read condition).

•The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 9- 16, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (for example, SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together.

The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note In burst read mode, during SLOE assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented.

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Contents Cypress Semiconductor Corporation CY7C68053 FeaturesBlock Diagram 8051 Microprocessor USB Signaling SpeedApplications Functional OverviewBuses USB Boot MethodsBus-powered Applications I2C BusPriority INT2VEC Value Source INT2 USB InterruptsCondition Reset and WakeupReset Timing Values Endpoint RAM Program/Data RAMRegister Addresses Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsGpif Default High-Speed Alternate Settings3External Fifo Interface 18 I2C Controller Autopointer AccessUSB Uploads and Downloads ECC Generation6Pin Assignments 18.2 I2C Interface Boot Load Access18.3 I2C Interface General Purpose Access CY7C68053 56-pin Vfbga Pin Assignment Top view Port a Name Type Default DescriptionCY7C68053 Pin Descriptions FX2LP18 Pin DescriptionsSLCS# FIFOADR0FIFOADR1 PktendFlagb IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flaga IFCONFIG10Ground FX2LP18 Register Summary Register SummaryECC2B1 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B0Gpifwf Gpifdone Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0INEP2CS EP1OUTCSBusy Stall EP1INCSEP2GPIFFLGSEL E6CFTC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0SEL AutoptrsetupDPL0 DPH0TH2 RCAP2LRCAP2H TL2Operating Conditions Absolute Maximum RatingsDC Characteristics USB Transceiver AC Electrical CharacteristicsGpif Synchronous Signals Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSloe Slrd Sequence DiagramSingle and Burst Synchronous Read Example IfclkSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Development Tool Kit Package DiagramOrdering Information PCB Layout Recommendations ARI Issue Date Orig. Description of ChangeDocument History OSG

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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