Cypress CY7C68053 E6CF, TC9 TC8, TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0, EP2GPIFFLGSEL, FS1 FS0, Nox

Page 20

CY7C68053

Table 5-1. FX2LP18 Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E6CF

1

GPIFTCB2[10]

GPIF Transaction Count

TC23

TC22

TC21

TC20

TC19

TC18

TC17

TC16

00000000

RW

 

 

 

Byte 2

 

 

 

 

 

 

 

 

 

 

E6D0

1

GPIFTCB1[10]

GPIF Transaction Count

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

00000000

RW

 

 

 

Byte 1

 

 

 

 

 

 

 

 

 

 

E6D1

1

GPIFTCB0[10]

GPIF Transaction Count

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

00000001

RW

 

 

 

Byte 0

 

 

 

 

 

 

 

 

 

 

 

2

Reserved

 

 

 

 

 

 

 

 

 

00000000

RW

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

E6D2

1

EP2GPIFFLGSEL[10]

Endpoint 2 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6D3

1

EP2GPIFPFSTOP

Endpoint 2 GPIF stop

0

0

0

0

0

0

0

FIFO2FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6D4

1

EP2GPIFTRIG[10]

Endpoint 2 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

E6DA

1

EP4GPIFFLGSEL[10]

Endpoint 4 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6DB

1

EP4GPIFPFSTOP

Endpoint 4 GPIF stop

0

0

0

0

0

0

0

FIFO4FLAG

00000000

RW

 

 

 

transaction on GPIF Flag

 

 

 

 

 

 

 

 

 

 

E6DC

1

EP4GPIFTRIG[10]

Endpoint 4 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

E6E2

1

EP6GPIFFLGSEL[10]

Endpoint 6 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6E3

1

EP6GPIFPFSTOP

Endpoint 6 GPIF stop

0

0

0

0

0

0

0

FIFO6FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6E4

1

EP6GPIFTRIG[10]

Endpoint 6 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

E6EA

1

EP8GPIFFLGSEL[10]

Endpoint 8 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6EB

1

EP8GPIFPFSTOP

Endpoint 8 GPIF stop

0

0

0

0

0

0

0

FIFO8FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6EC

1

EP8GPIFTRIG[10]

Endpoint 8 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

E6F0

1

XGPIFSGLDATH

GPIF Data H

D15

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx

RW

 

 

 

(16-bit mode only)

 

 

 

 

 

 

 

 

 

 

E6F1

1

XGPIFSGLDATLX

Read/Write GPIF Data L &

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

trigger transaction

 

 

 

 

 

 

 

 

 

 

E6F2

1

XGPIFSGLDATL-

Read GPIF Data L, no

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

 

 

NOX

transaction trigger

 

 

 

 

 

 

 

 

 

 

E6F3

1

GPIFREADYCFG

Internal RDY, Sync/Async,

INTRDY

SAS

TCXRDY5

0

0

0

0

0

00000000

bbbrrrrr

 

 

 

RDY pin states

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E6F4

1

GPIFREADYSTAT

GPIF Ready Status

0

0

0

0

0

0

RDY1

RDY0

00xxxxxx

R

E6F5

1

GPIFABORT

Abort GPIF Waveforms

x

x

x

x

x

x

x

x

xxxxxxxx

W

E6F6

2

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

ENDPOINT BUFFERS

 

 

 

 

 

 

 

 

 

 

 

E740

64

EP0BUF

EP0-IN/-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E780

64

EP10UTBUF

EP1-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E7C0

64

EP1INBUF

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E800

2048

Reserved

 

 

 

 

 

 

 

 

 

 

RW

F000

1024

EP2FIFOBUF

512/1024-byte EP 2/slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

FIFO buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

F400

512

EP4FIFOBUF

512 byte EP 4/slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

F600

512

Reserved

 

 

 

 

 

 

 

 

 

 

 

F800

1024

EP6FIFOBUF

512/1024-byte EP 6/slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

FIFO buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

FC00

512

EP8FIFOBUF

512 byte EP 8/slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

FE00

512

Reserved

 

 

 

 

 

 

 

 

 

 

 

xxxx

 

I²C Configuration Byte

 

0

DISCON

0

0

0

0

0

400KHZ

xxxxxxxx

n/a

 

 

 

 

 

 

 

 

 

 

 

 

[13]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Special Function Registers (SFRs)

 

 

 

 

 

 

 

 

 

 

80

1

IOA[12]

Port A (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

Notes

12.SFRs not part of the standard 8051 architecture.

13.If no EEPROM is detected by the SIE then the default is 00000000.

Document # 001-06120 Rev *F

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Contents Cypress Semiconductor Corporation CY7C68053 FeaturesBlock Diagram USB Signaling Speed ApplicationsFunctional Overview 8051 MicroprocessorUSB Boot Methods Bus-powered ApplicationsI2C Bus BusesINT2 USB Interrupts Priority INT2VEC Value SourceCondition Reset and WakeupReset Timing Values Endpoint RAM Program/Data RAMRegister Addresses Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Gpif Default High-Speed Alternate Settings3External Fifo Interface Autopointer Access USB Uploads and DownloadsECC Generation6 18 I2C ControllerPin Assignments 18.2 I2C Interface Boot Load Access18.3 I2C Interface General Purpose Access CY7C68053 56-pin Vfbga Pin Assignment Top view Name Type Default Description CY7C68053 Pin DescriptionsFX2LP18 Pin Descriptions Port aFIFOADR0 FIFOADR1Pktend SLCS#Slrd IFCONFIG10 Slwr IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC1B2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16ECC2B0 ECC2B1Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0 EpieEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneEP1OUTCS Busy StallEP1INCS EP2CSE6CF TC9 TC8TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELAutoptrsetup DPL0DPH0 SELRCAP2L RCAP2HTL2 TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics USB Transceiver AC Electrical CharacteristicsGpif Synchronous Signals Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSequence Diagram Single and Burst Synchronous Read ExampleIfclk Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Development Tool Kit Package DiagramOrdering Information PCB Layout Recommendations Issue Date Orig. Description of Change Document HistoryOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.