Cypress CY7C68053 manual FIFOADR0, FIFOADR1, Pktend, Slcs#, Port B

Page 13

CY7C68053

Table 4-1. FX2LP18 Pin Descriptions (continued)[9]

56 VFBGA

Name

Type

Default

Description

6F

PA4 or

I/O/Z

I

Multiplexed pin whose function is selected by:

 

FIFOADR0

 

(PA4)

IFCONFIG[1:0].

 

 

 

 

PA4 is a bidirectional IO port pin.

 

 

 

 

FIFOADR0 is an input-only address select for the slave FIFO’s connected

 

 

 

 

to FD[7:0] or FD[15:0].

8C

PA5 or

I/O/Z

I

Multiplexed pin whose function is selected by:

 

FIFOADR1

 

(PA5)

IFCONFIG[1:0].

 

 

 

 

PA5 is a bidirectional IO port pin.

 

 

 

 

FIFOADR1 is an input-only address select for the slave FIFO’s connected

 

 

 

 

to FD[7:0] or FD[15:0].

7C

PA6 or

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.

 

PKTEND

 

(PA6)

PA6 is a bidirectional IO port pin.

 

 

 

 

PKTEND is an input used to commit the FIFO packet data to the endpoint

 

 

 

 

and whose polarity is programmable using FIFOPINPOLAR.5.

6C

PA7 or

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

 

FLAGD or

 

(PA7)

PORTACFG.7 bits.

 

SLCS#

 

 

PA7 is a bidirectional IO port pin.

 

 

 

 

FLAGD is a programmable slave FIFO output status flag signal.

 

 

 

 

SLCS# gates all other slave FIFO enable/strobes

Port B

 

 

 

 

 

 

 

 

 

3H

PB0 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[0]

 

(PB0)

IFCONFIG[1:0].

 

 

 

 

PB0 is a bidirectional IO port pin.

 

 

 

 

FD[0] is the bidirectional FIFO/GPIF data bus.

4F

PB1 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[1]

 

(PB1)

IFCONFIG[1:0].

 

 

 

 

PB1 is a bidirectional IO port pin.

 

 

 

 

FD[1] is the bidirectional FIFO/GPIF data bus.

4H

PB2 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[2]

 

(PB2)

IFCONFIG[1:0].

 

 

 

 

PB2 is a bidirectional IO port pin.

 

 

 

 

FD[2] is the bidirectional FIFO/GPIF data bus.

4G

PB3 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[3]

 

(PB3)

IFCONFIG[1:0].

 

 

 

 

PB3 is a bidirectional IO port pin.

 

 

 

 

FD[3] is the bidirectional FIFO/GPIF data bus.

5H

PB4 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[4]

 

(PB4)

IFCONFIG[1:0].

 

 

 

 

PB4 is a bidirectional IO port pin.

 

 

 

 

FD[4] is the bidirectional FIFO/GPIF data bus.

5G

PB5 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[5]

 

(PB5)

IFCONFIG[1:0].

 

 

 

 

PB5 is a bidirectional IO port pin.

 

 

 

 

FD[5] is the bidirectional FIFO/GPIF data bus.

5F

PB6 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[6]

 

(PB6)

IFCONFIG[1:0].

 

 

 

 

PB6 is a bidirectional IO port pin.

 

 

 

 

FD[6] is the bidirectional FIFO/GPIF data bus.

6H

PB7 or

I/O/Z

I

Multiplexed pin whose function is selected by the following bits:

 

FD[7]

 

(PB7)

IFCONFIG[1:0].

 

 

 

 

PB7 is a bidirectional IO port pin.

 

 

 

 

FD[7] is the bidirectional FIFO/GPIF data bus.

Document # 001-06120 Rev *F

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Contents Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation Applications USB Signaling SpeedFunctional Overview 8051 MicroprocessorBus-powered Applications USB Boot MethodsI2C Bus BusesPriority INT2VEC Value Source INT2 USB InterruptsReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsExternal Fifo Interface Default High-Speed Alternate Settings3Gpif USB Uploads and Downloads Autopointer AccessECC Generation6 18 I2C Controller18.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view CY7C68053 Pin Descriptions Name Type Default DescriptionFX2LP18 Pin Descriptions Port aFIFOADR1 FIFOADR0Pktend SLCS#Slwr IFCONFIG10 Slrd IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground FX2LP18 Register Summary Register SummaryCOL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC1B2ECC2B0 ECC2B1Epie Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneBusy Stall EP1OUTCSEP1INCS EP2CSTC9 TC8 E6CFTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELDPL0 AutoptrsetupDPH0 SELRCAP2H RCAP2LTL2 TH2Operating Conditions Absolute Maximum RatingsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSingle and Burst Synchronous Read Example Sequence DiagramIfclk Sloe SlrdSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations Document History Issue Date Orig. Description of ChangeOSG ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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