Cypress CY7C68053 manual Program/Data RAM, Register Addresses, Endpoint RAM

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CY7C68053

Figure 3-3. FX2LP18 Internal Code Memory

 

 

FFFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.5 kBytes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB regs and

 

 

 

 

 

 

 

 

 

4K FIFO buffers

 

 

 

 

 

 

E200

 

 

 

 

 

 

 

E1FF

0.5 kBytes RAM

 

 

 

 

 

 

E000

Data

 

 

 

 

 

 

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3FFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kBytes RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0000

 

 

Code and Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.10

Program/Data RAM

This section describes the FX2LP18 RAM.

3.10.1Size

The FX2LP18 has 16 kBytes of internal program/data RAM. No USB control registers appear in this space.

Memory maps are shown in Figure 3-3and Figure 3-4.

3.10.2Internal Code Memory

This mode implements the internal 16-kByte block of RAM (starting at 0) as combined code and data memory. Only the internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces have the following access:

•USB download

•USB upload

•Set-up data pointer

•I2C interface boot load

3.11Register Addresses

Figure 3-4. Register Address Memory

 

FFFF

4 kBytes EP2-EP8

 

 

 

 

buffers

 

 

(8 x 512)

 

F000

 

 

EFFF

 

 

 

2 kBytes RESERVED

 

E800

 

 

E7FF

64 Bytes EP1IN

 

E7C0

 

 

 

E7BF

64 Bytes EP1OUT

 

E780

 

 

 

E77F

64 Bytes EP0 IN/OUT

 

E740

 

 

 

E73F

64 Bytes RESERVED

 

E700

 

 

 

E6FF

8051 Addressable Registers

 

 

 

E500

(512)

 

 

 

E4FF

Reserved (128)

 

E480

 

 

 

E47F

128 Bytes GPIF Waveforms

 

E400

 

 

 

E3FF

Reserved (512)

 

E200

 

 

 

E1FF

 

 

 

512 Bytes

 

E000

8051 xdata RAM

 

 

3.12Endpoint RAM

This section describes the FX2LP18 Endpoint RAM.

3.12.1Size

• 3 × 64 bytes (Endpoints 0, 1)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

3.12.2Organization

• EP0

• Bidirectional endpoint zero, 64-byte buffer

• EP1IN, EP1OUT

• 64-byte buffers: bulk or interrupt

• EP2, 4, 6, 8

•Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be double, triple, or quad buffered. For high-speed endpoint configuration options, see Figure 3-5.

3.12.3Set-up Data Buffer

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the set-up data from a CONTROL transfer.

3.12.4Endpoint Configurations (High-speed Mode)

Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any one of the 12 configurations shown in the

Document # 001-06120 Rev *F

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Contents CY7C68053 Features Block DiagramCypress Semiconductor Corporation Functional Overview USB Signaling SpeedApplications 8051 MicroprocessorI2C Bus USB Boot MethodsBus-powered Applications BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset and Wakeup Reset Timing ValuesCondition Program/Data RAM Register AddressesEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3Default High-Speed Alternate Settings3 External Fifo InterfaceGpif ECC Generation6 Autopointer AccessUSB Uploads and Downloads 18 I2C Controller18.2 I2C Interface Boot Load Access 18.3 I2C Interface General Purpose AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view FX2LP18 Pin Descriptions Name Type Default DescriptionCY7C68053 Pin Descriptions Port aPktend FIFOADR0FIFOADR1 SLCS#Flaga IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC2B0 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B1EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie Gpifwf GpifdoneEP1INCS EP1OUTCSBusy Stall EP2CSTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 E6CFTC9 TC8 EP2GPIFFLGSELDPH0 AutoptrsetupDPL0 SELTL2 RCAP2LRCAP2H TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics AC Electrical Characteristics Gpif Synchronous SignalsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressIfclk Sequence DiagramSingle and Burst Synchronous Read Example Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Package Diagram Ordering InformationDevelopment Tool Kit PCB Layout Recommendations OSG Issue Date Orig. Description of ChangeDocument History ARI

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.
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