Diamond Power Products MM-48-AT user manual Performing AN A/D Conversion

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8. PERFORMING AN A/D CONVERSION

This chapter describes the steps involved in performing an A/D conversion on a selected input channel using direct programming (not with the driver software). This describes the basic operation of a single A/D conversion without interrupts. For a more complete description including interrupts and all register control bits, see chapter 9.

There are five steps involved in performing an A/D conversion:

1.Select the input channel

2.Wait for analog input circuit to settle

3.Trigger an A/D conversion

4.Wait for the conversion to finish

5.Read the data from the board

6.Convert the numerical data to a meaningful value

8.1Select the input channel

To select the input channel to read, write a low-channel/high-channel pair to the channel register at base + 2. (See Chapter 6). The low 4 bits select the low channel, and the high 4 bits select the high channel. When you write any value to this register, the current A/D channel is set to the low channel.

For example:

To set the board to channel 4 only, write 0x44 to Base + 2.

To set the board to read channels 0 through 15, write 0xF0 to Base + 2.

⇒Note: When you perform an A/D conversion, the current channel is automatically incremented to the next channel in the selected range. Therefore, to perform A/D conversions on a group of consecutively-numbered channels, you do not need to write the input channel prior to each conversion. For example, to read from channels 0 - 2, write Hex 20 to base + 2. The first conversion is on channel 0, the second will be on channel 1, and the third will be on channel 2. Then the channel counter wraps around to the beginning again, so the fourth conversion will be on channel 0 again, and so on.

If you are sampling the same channel repeatedly, then you set both high and low to the same value as in the first example above. Then on subsequent conversions you do not need to set the channel again.

8.2 Wait for analog input circuit to settle

After writing to the channel register (Base + 2), you must allow time for the analog input circuit to settle before starting an A/D conversion. The board has a built-in 10∝s timer to assist with the wait period. Monitor the ADBUSY bit at Base + 9 bit 7. When it is 1 the circuit is actively settling on the input signal, or else the board is currently performing and A/D conversion or scan. When it is 0 the board is ready to perform A/D conversions.

Diamond-MM-48-AT User Manual V1.01

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Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing O Header Pinout and PIN Description Signal Name DefinitionJ3 Analog and Digital I/O J4 Relays and Optocouplers Signal Name Definition Relay output contactsOptoisolated input contacts Board Configuration Base AddressBase Address Jumper Position Hex Decimal Interrupt Level SelectionReserved Optocoupler PolarityAnalog Input Range Base + Write Function Read Function OverviewLSB MSB Register Map Bit Assignments Write operationsDA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Read operationsRegister Definitions Base + WriteDefinitions Base + ReadBase + Read/Write A/D Channel Register AD9 AD8HIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 Base + Read/Write Digital I/O Configuration Register Base + Read/Write Relay Control PortRELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 DIR3 DIR2 DIR1 DIR0DIO3 DIO2 DIO1 DIO0 Base + Read Digital I/O Data and Edge StatusDEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0Daupdt DACH2 DACH1 DACH0 Base + Write Channel and Control RegisterOEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Command Register Dapre Daprld Reset Fiforst AdstartBase + Read Status Register POL ADCH3 ADCH2 ADCH1 ADCH0Base + Write Configuration Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Configuration & Status Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Write Fifo Control Register Fifoth Fifoen ScanenBase + Read Fifo Status Register OVF Fifoth Fifoen ScanenBase + Write Interrupt Control Register Clrt Clrd Clro Clra Tinte Dinte Ointe AinteBase + Read Interrupt Status Register Tint Dint Oint Aint Tinte Dinte Ointe AinteBase + Read/Write Counter/Timer D15 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D23 Ctrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Write Counter/Timer Control RegisterCtrno Base + Read/Write Eeprom / TrimDAC Data Register Base + Read/Write Eeprom / TrimDAC Address RegisterBase + Write Eeprom Access Key Register Base + Write Calibration Control RegisterBase + Read Calibration Status Register Base + Read Fpga Revision CodeAnalog Input Ranges and Resolution ResolutionInput Ranges Single Ended and Differential InputsPerforming AN A/D Conversion Trigger an A/D conversion on the current channel LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSBInput voltage = A/D value / 32768 * Full-scale voltage D SCAN, FIFO, and Interrupt Operation TriggerClken Clksel Conversion or ScanFifo Operation Interrupt OperationFifoen Fifoth Scanen Fifoen =Operation Table Guidelines for Selecting Fifo Use Fifoen and FifothAinte Fifoen Scanen Analog Output Overview Generating AN Analog Output Autocalibration Operation Reference Voltages12.2 A/D calibration 12.3 D/A CalibrationDigital I/O Operation Procedure for enabling interrupts on selected edges Optocoupler OperationEdge detection assumes OENn = 1 to enable edge detection Polarity and logic readbackRelay Operation Counter 0 A/D Sample Control COUNTER/TIMER OperationCounter 1 Counting/Totalizing Functions Command Sequences CounterCounter Outpbase+15,0x01 Outpbase+15,0x81 Autocalibration SpecificationsGeneral
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