Diamond Power Products MM-48-AT Fifo Operation, Interrupt Operation, Fifoen Fifoth Scanen

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FIFO Operation

After each A/D conversion is completed, the A/D data is stored in the FIFO. The data is inserted in LSB / MSB sequence. The FIFO holds 4096 bytes, or 2048 samples. It has several flags that indicate its state:

EF

Empty flag

1 when the FIFO is empty and 0 otherwise.

8F

1/8 full flag

1 when the FIFO has 256 or more samples, 0 otherwise

HF

Half full

1 when the FIFO has 2048 or more bytes of data (1024 or more

 

 

samples), 0 otherwise

FF

Full flag

1 when the FIFO has 4096 bytes (2048 samples), 0 otherwise

OVF

Overflow flag

1 when the FIFO is full and the board attempts to store a new A/D

 

 

sample in the FIFO. This indicates an error condition. The new A/D

 

 

data will not be stored in the FIFO and will be lost. The current

 

 

contents of the FIFO will be preserved.

If OVF is set, the only way to clear it is to reset the FIFO by writing a 1 to the FIFORST bit in register 8. Generally the data would be read out before resetting the FIFO.

Interrupt Operation

If AINTE is set, the board will generate an interrupt when the selected condition occurs, as determined by the control bits FIFOEN, FIFOTH, and SCANEN. The table below describes the timing of interrupts and the expected performance of the application software’s interrupt routine (including Diamond Systems’ Universal Driver software). Note that in all cases, A/D data is stored in and read from the FIFO, regardless of the FIFOEN setting. FIFOEN only controls whether the FIFO flags are used to drive interrupt requests.

FIFOEN

FIFOTH

SCANEN

Interrupt Operation

 

0

0

0

Interrupt occurs at the end of each individual A/D

 

 

 

conversion. Interrupt routine reads one A/D sample from

 

 

 

the board.

 

0

0

1

Interrupt occurs at the end of each A/D scan. Interrupt

 

 

 

routine reads one complete scan from the board.

 

0

1

0

Same as case 0 0 0 above. FIFOTH is ignored when

 

 

 

FIFOEN = 0.

 

0

1

1

Same as case 0 0 1 above. FIFOTH is ignored when

 

 

 

FIFOEN = 0.

 

1

0

0

Interrupt occurs when 1024 A/D conversions are

 

 

 

complete. Interrupt routine reads 1024 samples from the

 

 

 

FIFO.

 

1

0

1

Interrupt occurs when 1024 A/D conversions are

 

 

 

complete AND the current A/D scan is complete (total

 

 

 

no. of conversions may be greater than 1024). Interrupt

 

 

 

routine reads enough scans from the A/D FIFO to equal

 

 

 

or exceed 1024 samples.

 

1

1

0

Interrupt occurs when 256 A/D conversions are

 

 

 

complete. Interrupt routine reads 256 samples from the

 

 

 

FIFO.

 

1

1

1

Interrupt occurs when 256 A/D conversions are

 

 

 

complete AND the current A/D scan is complete (total

 

 

 

no. of conversions may be greater than 256). Interrupt

 

 

 

routine reads enough scans from the A/D FIFO to equal

 

 

 

or exceed 256 samples.

 

 

 

 

Diamond-MM-48-AT User Manual V1.01

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Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing J3 Analog and Digital I/O Signal Name DefinitionO Header Pinout and PIN Description Optoisolated input contacts Signal Name Definition Relay output contactsJ4 Relays and Optocouplers Board Configuration Base AddressBase Address Jumper Position Hex Decimal Interrupt Level SelectionAnalog Input Range Optocoupler PolarityReserved LSB MSB OverviewBase + Write Function Read Function Register Map Bit Assignments Write operationsDA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Read operationsRegister Definitions Base + WriteDefinitions Base + ReadHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 AD9 AD8Base + Read/Write A/D Channel Register Base + Read/Write Digital I/O Configuration Register Base + Read/Write Relay Control PortRELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 DIR3 DIR2 DIR1 DIR0DIO3 DIO2 DIO1 DIO0 Base + Read Digital I/O Data and Edge StatusDEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Channel and Control RegisterDaupdt DACH2 DACH1 DACH0 Base + Write Command Register Dapre Daprld Reset Fiforst AdstartBase + Read Status Register POL ADCH3 ADCH2 ADCH1 ADCH0Base + Write Configuration Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Configuration & Status Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Write Fifo Control Register Fifoth Fifoen ScanenBase + Read Fifo Status Register OVF Fifoth Fifoen ScanenBase + Write Interrupt Control Register Clrt Clrd Clro Clra Tinte Dinte Ointe AinteBase + Read Interrupt Status Register Tint Dint Oint Aint Tinte Dinte Ointe AinteBase + Read/Write Counter/Timer D23 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D15 Ctrno Base + Write Counter/Timer Control RegisterCtrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Read/Write Eeprom / TrimDAC Data Register Base + Read/Write Eeprom / TrimDAC Address RegisterBase + Write Eeprom Access Key Register Base + Write Calibration Control RegisterBase + Read Calibration Status Register Base + Read Fpga Revision CodeAnalog Input Ranges and Resolution ResolutionInput Ranges Single Ended and Differential InputsPerforming AN A/D Conversion Trigger an A/D conversion on the current channel LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSBInput voltage = A/D value / 32768 * Full-scale voltage D SCAN, FIFO, and Interrupt Operation TriggerClken Clksel Conversion or ScanFifo Operation Interrupt OperationFifoen Fifoth Scanen Fifoen =Ainte Fifoen Scanen Guidelines for Selecting Fifo Use Fifoen and FifothOperation Table Analog Output Overview Generating AN Analog Output Autocalibration Operation Reference Voltages12.2 A/D calibration 12.3 D/A CalibrationDigital I/O Operation Procedure for enabling interrupts on selected edges Optocoupler OperationEdge detection assumes OENn = 1 to enable edge detection Polarity and logic readbackRelay Operation Counter 1 Counting/Totalizing Functions COUNTER/TIMER OperationCounter 0 A/D Sample Control Command Sequences CounterCounter Outpbase+15,0x01 Outpbase+15,0x81 General SpecificationsAutocalibration
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