Diamond Power Products MM-48-AT Base + Write Fifo Control Register, Fifoth Fifoen Scanen

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Base + 10		Write			FIFO Control Register

Bit No.		7		6		5	4	3	2	1	0

Name								PAGE	FIFOTH	FIFOEN	SCANEN

PAGE		Page number for registers at Base + 12 through Base + 15
		Page 0:			82C54 counter/timer access
		Page 1:			Calibration registers
FIFOTH		FIFO threshold: 0 = 1024 samples (half full), 1 = 256 samples (1/8 full)
FIFOEN		FIFO enable:

1Enable FIFO operation; if interrupts are enabled, interrupt requests will occur when the FIFO reaches or exceeds the threshold selected with FIFOTH.

0Disable FIFO operation; if interrupts are enabled, interrupts will occur after each A/D conversion or scan is completed.

SCANEN Scan enable:

1A/D scan mode enabled; FIFO will fill up with data for a single scan, and ADBUSY will stay high until an entire scan is complete. If interrupts are enabled, interrupts will occur at the end of the scan. If FIFOEN = 1 and SCANEN = 1, the interrupt will occur at the end of the scan that causes the FIFO to reach or exceed its half-full point (256 samples).

0Scan mode disabled; the ADBUSY bit will remain high for a single conversion

Base + 10

Read

FIFO Status Register

Bit No.

7

6

5

4

3

2

1

0

Name

OVF

HF

8F

EF

PAGE

FIFOTH

FIFOEN

SCANEN

OVF

FIFO overflow flag: 0 = no overflow, 1 = overflow

Overflow is defined as the state when the FIFO is full and another A/D

conversion occurs before any data is read out of the FIFO. In an overflow

condition the FIFO contents are preserved, and no new data will be written to the

FIFO. To clear an overflow condition, the FIFO must be reset with the FIFORST

bit in register 8.

8F

FIFO 1/8 full flag:

0

FIFO is less than 1/8 full (256 samples)

1

FIFO is greater than or equal to 1/8 full

HF

FIFO half full flag

0

FIFO is less than half full (1024 or less samples)

1

FIFO is greater than half full (1025 or more samples)

EF

FIFO empty flag: 0 = FIFO is not empty, 1 = FIFO is empty

PAGE

Readback of PAGE bit described above

FIFOTH

Readback of FIFO threshold bit described above

FIFOEN

Readback of FIFOEN bit described above

SCANEN

Readback of SCANEN bit described above

Diamond-MM-48-AT User Manual V1.01

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Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing J3 Analog and Digital I/O Signal Name DefinitionO Header Pinout and PIN Description Optoisolated input contacts Signal Name Definition Relay output contactsJ4 Relays and Optocouplers Board Configuration Base AddressBase Address Jumper Position Hex Decimal Interrupt Level SelectionAnalog Input Range Optocoupler PolarityReserved LSB MSB OverviewBase + Write Function Read Function Register Map Bit Assignments Write operationsDA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Read operationsRegister Definitions Base + WriteDefinitions Base + ReadHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 AD9 AD8Base + Read/Write A/D Channel Register Base + Read/Write Digital I/O Configuration Register Base + Read/Write Relay Control PortRELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 DIR3 DIR2 DIR1 DIR0DIO3 DIO2 DIO1 DIO0 Base + Read Digital I/O Data and Edge StatusDEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Channel and Control RegisterDaupdt DACH2 DACH1 DACH0 Base + Write Command Register Dapre Daprld Reset Fiforst AdstartBase + Read Status Register POL ADCH3 ADCH2 ADCH1 ADCH0Base + Write Configuration Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Configuration & Status Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Write Fifo Control Register Fifoth Fifoen ScanenBase + Read Fifo Status Register OVF Fifoth Fifoen ScanenBase + Write Interrupt Control Register Clrt Clrd Clro Clra Tinte Dinte Ointe AinteBase + Read Interrupt Status Register Tint Dint Oint Aint Tinte Dinte Ointe AinteBase + Read/Write Counter/Timer D23 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D15 Ctrno Base + Write Counter/Timer Control RegisterCtrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Read/Write Eeprom / TrimDAC Data Register Base + Read/Write Eeprom / TrimDAC Address RegisterBase + Write Eeprom Access Key Register Base + Write Calibration Control RegisterBase + Read Calibration Status Register Base + Read Fpga Revision CodeAnalog Input Ranges and Resolution ResolutionInput Ranges Single Ended and Differential InputsPerforming AN A/D Conversion Trigger an A/D conversion on the current channel LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSBInput voltage = A/D value / 32768 * Full-scale voltage D SCAN, FIFO, and Interrupt Operation TriggerClken Clksel Conversion or ScanFifo Operation Interrupt OperationFifoen Fifoth Scanen Fifoen =Ainte Fifoen Scanen Guidelines for Selecting Fifo Use Fifoen and FifothOperation Table Analog Output Overview Generating AN Analog Output Autocalibration Operation Reference Voltages12.2 A/D calibration 12.3 D/A CalibrationDigital I/O Operation Procedure for enabling interrupts on selected edges Optocoupler OperationEdge detection assumes OENn = 1 to enable edge detection Polarity and logic readbackRelay Operation Counter 1 Counting/Totalizing Functions COUNTER/TIMER OperationCounter 0 A/D Sample Control Command Sequences CounterCounter Outpbase+15,0x01 Outpbase+15,0x81 General SpecificationsAutocalibration