Diamond Power Products MM-48-AT user manual Base + Write Interrupt Control Register

Page 21

Base + 11

Write

 

Interrupt Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

 

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

Name

CLRT

CLRD

 

CLRO

 

CLRA

TINTE

DINTE

OINTE

 

AINTE

 

 

 

 

 

 

 

 

 

 

 

CLRT

Clear the timer interrupt flip flop.

 

 

 

 

 

 

CLRD

Clear the digital input interrupt flip flop and reset their edge detect status bits.

 

CLRO

Clear the optocoupler input interrupt flip flop and reset their edge detect status

 

bits.

 

 

 

 

 

 

 

 

 

 

CLRA

Clear the analog input interrupt flip flop.

 

 

 

 

 

The interrupt flip flop for each circuit is set whenever an interrupt request is generated by that circuit, and it must be cleared by software before another interrupt of that type can be generated. An interrupt request from one or more circuits will generate an interrupt request on the selected IRQ line. Writing a 1 to any CLRx bit clears the interrupt flip flop for that circuit and leaves alone all other bits in this register. Writing a 0 to a CLRx bit has no effect on that circuit. Each circuit’s interrupt flip flop can be reset individually. When all interrupt circuits have been reset, either by clearing them individually or by disabling them with xINTE = 0, the board’s interrupt request line will be tristated.

TINTE

Timer interrupt enable:

 

1

Enable interrupts on falling edge of timer 1

 

0

Disable timer interrupts

DINTE

Digital I/O interrupt enable:

 

1

Enable interrupts on any change of state of DIO3-0

 

0

Disable digital input interrupts

OINTE

Optocoupler input interrupt enable:

 

1

Enable optocoupler interrupts on change of state determined by register 6; in

 

 

order for an interrupt to occur, OINTE must be set to 1, at least one of OEN3-

 

 

0 must also be set to 1, and the edge indicated by the corresponding bit

 

 

POL3-0 must occur on the selected optocoupler.

 

0

Disable optocoupler interrupts

AINTE

Analog input interrupt enable:

 

1

Enable A/D interrupts

 

0

Disable A/D interrupts

Diamond-MM-48-AT User Manual V1.01

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Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing Signal Name Definition O Header Pinout and PIN DescriptionJ3 Analog and Digital I/O Signal Name Definition Relay output contacts J4 Relays and OptocouplersOptoisolated input contacts Base Address Board ConfigurationBase Address Jumper Position Hex Decimal Interrupt Level SelectionOptocoupler Polarity ReservedAnalog Input Range Overview Base + Write Function Read FunctionLSB MSB Write operations Register Map Bit AssignmentsDA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Read operationsBase + Write Register DefinitionsDefinitions Base + ReadAD9 AD8 Base + Read/Write A/D Channel RegisterHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 Base + Read/Write Relay Control Port Base + Read/Write Digital I/O Configuration RegisterRELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 DIR3 DIR2 DIR1 DIR0Base + Read Digital I/O Data and Edge Status DIO3 DIO2 DIO1 DIO0DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0Base + Write Channel and Control Register Daupdt DACH2 DACH1 DACH0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Dapre Daprld Reset Fiforst Adstart Base + Write Command RegisterPOL ADCH3 ADCH2 ADCH1 ADCH0 Base + Read Status RegisterCKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Write Configuration RegisterAdbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Read Configuration & Status RegisterFifoth Fifoen Scanen Base + Write Fifo Control RegisterBase + Read Fifo Status Register OVF Fifoth Fifoen ScanenClrt Clrd Clro Clra Tinte Dinte Ointe Ainte Base + Write Interrupt Control RegisterTint Dint Oint Aint Tinte Dinte Ointe Ainte Base + Read Interrupt Status RegisterBase + Read/Write Counter/Timer D7 Base + Read/Write Counter/Timer D15Base + Read/Write Counter/Timer D23 Base + Write Counter/Timer Control Register Ctrno Latch Gtdis Gten Ctdis Cten Load CLRCtrno Base + Read/Write Eeprom / TrimDAC Address Register Base + Read/Write Eeprom / TrimDAC Data RegisterBase + Write Calibration Control Register Base + Write Eeprom Access Key RegisterBase + Read Calibration Status Register Base + Read Fpga Revision CodeResolution Analog Input Ranges and ResolutionInput Ranges Single Ended and Differential InputsPerforming AN A/D Conversion LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSB Trigger an A/D conversion on the current channelInput voltage = A/D value / 32768 * Full-scale voltage Trigger D SCAN, FIFO, and Interrupt OperationClken Clksel Conversion or ScanInterrupt Operation Fifo OperationFifoen Fifoth Scanen Fifoen =Guidelines for Selecting Fifo Use Fifoen and Fifoth Operation TableAinte Fifoen Scanen Analog Output Overview Generating AN Analog Output Reference Voltages Autocalibration Operation12.2 A/D calibration 12.3 D/A CalibrationDigital I/O Operation Optocoupler Operation Procedure for enabling interrupts on selected edgesPolarity and logic readback Edge detection assumes OENn = 1 to enable edge detectionRelay Operation COUNTER/TIMER Operation Counter 0 A/D Sample ControlCounter 1 Counting/Totalizing Functions Counter Command SequencesCounter Outpbase+15,0x01 Outpbase+15,0x81 Specifications AutocalibrationGeneral
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