Diamond Power Products MM-48-AT user manual Base + Read/Write Counter/Timer D7

Page 23

Page 0: Counter/Timer

Base + 12

Read/Write

Counter/Timer D7 - 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

D7

D6

 

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

 

 

This register is used for both Counter 0 and Counter 1. It is the LSB for both counters.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s LSB register will be loaded with this value.

When reading from this register, the LSB value of the most recent Latch command will be returned. The value returned is NOT the value written to this register.

Base + 13

Read/Write

Counter/Timer D15 - 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

D15

D14

 

D13

D12

 

D11

D10

D9

D8

 

 

 

 

 

 

 

 

 

 

 

This register is used for both Counter 0 and Counter 1. It is the MSB for counter 1 and the middle byte for counter 0.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s associated register will be loaded with this value. For counter 0, it is the middle byte. For counter 1, it is the MSB.

When reading from this register, the associated byte of the most recent Latch command will be returned. The value returned is NOT the value written to this register.

Base + 14

Read/Write

Counter/Timer D23 - 16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

D23

D22

 

D21

D20

 

D19

D18

D17

D16

 

 

 

 

 

 

 

 

 

 

 

This register is used for Counter 0 only. Counter 0 is 24 bits wide, while Counter 1 is only 16 bits wide.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15 for Counter 0, the counter’s MSB register will be loaded with this value. When issuing a Load command for counter 1, this register is ignored.

When reading from this register, the MSB value of the most recent Latch command for counter 0 will be returned. The value returned is NOT the value written to this register.

Diamond-MM-48-AT User Manual V1.01

Page 23

Image 23
Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing J3 Analog and Digital I/O Signal Name DefinitionO Header Pinout and PIN Description Optoisolated input contacts Signal Name Definition Relay output contactsJ4 Relays and Optocouplers Interrupt Level Selection Board ConfigurationBase Address Base Address Jumper Position Hex DecimalAnalog Input Range Optocoupler PolarityReserved LSB MSB OverviewBase + Write Function Read Function Read operations Register Map Bit AssignmentsWrite operations DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0Base + Read Register DefinitionsBase + Write DefinitionsHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 AD9 AD8Base + Read/Write A/D Channel Register DIR3 DIR2 DIR1 DIR0 Base + Read/Write Digital I/O Configuration RegisterBase + Read/Write Relay Control Port RELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0 DIO3 DIO2 DIO1 DIO0Base + Read Digital I/O Data and Edge Status DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Channel and Control RegisterDaupdt DACH2 DACH1 DACH0 Dapre Daprld Reset Fiforst Adstart Base + Write Command RegisterPOL ADCH3 ADCH2 ADCH1 ADCH0 Base + Read Status RegisterCKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Write Configuration RegisterAdbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Read Configuration & Status RegisterOVF Fifoth Fifoen Scanen Base + Write Fifo Control RegisterFifoth Fifoen Scanen Base + Read Fifo Status RegisterClrt Clrd Clro Clra Tinte Dinte Ointe Ainte Base + Write Interrupt Control RegisterTint Dint Oint Aint Tinte Dinte Ointe Ainte Base + Read Interrupt Status RegisterBase + Read/Write Counter/Timer D23 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D15 Ctrno Base + Write Counter/Timer Control RegisterCtrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Read/Write Eeprom / TrimDAC Address Register Base + Read/Write Eeprom / TrimDAC Data RegisterBase + Read Fpga Revision Code Base + Write Eeprom Access Key RegisterBase + Write Calibration Control Register Base + Read Calibration Status RegisterSingle Ended and Differential Inputs Analog Input Ranges and ResolutionResolution Input RangesPerforming AN A/D Conversion LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSB Trigger an A/D conversion on the current channelInput voltage = A/D value / 32768 * Full-scale voltage Conversion or Scan D SCAN, FIFO, and Interrupt OperationTrigger Clken ClkselFifoen = Fifo OperationInterrupt Operation Fifoen Fifoth ScanenAinte Fifoen Scanen Guidelines for Selecting Fifo Use Fifoen and FifothOperation Table Analog Output Overview Generating AN Analog Output 12.3 D/A Calibration Autocalibration OperationReference Voltages 12.2 A/D calibrationDigital I/O Operation Optocoupler Operation Procedure for enabling interrupts on selected edgesPolarity and logic readback Edge detection assumes OENn = 1 to enable edge detectionRelay Operation Counter 1 Counting/Totalizing Functions COUNTER/TIMER OperationCounter 0 A/D Sample Control Counter Command SequencesCounter Outpbase+15,0x01 Outpbase+15,0x81 General SpecificationsAutocalibration