Diamond Power Products MM-48-AT D SCAN, FIFO, and Interrupt Operation, Trigger, Clken Clksel

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9. A/D SCAN, FIFO, AND INTERRUPT OPERATION

This chapter describes in detail the interrupt performance of the A/D circuit under all conditions.

The control bits FIFOEN (FIFO enable), FIFOTH (FIFO threshold), SCANEN (scan enable), SCNINT (scan interval), and AINTE (A/D interrupt enable) determine the behavior of the board during A/D conversions with interrupts. Control bits CLKEN and CLKSEL determine the source of the A/D trigger, either software, on-board counter/timer, or external signal.

In all cases, at the end of an AD conversion A/D data is latched into the FIFO in an interleaved fashion, first LSB, then MSB. A/D Data is read out of the FIFO with 2 read operations, first Base + 0 (LSB) and then Base + 1 (MSB).

When SCANEN = 1, each time an A/D trigger occurs, the board will perform an A/D conversion on all channels in the channel range. The time between A/D conversions is determined by the setting of the SCNINT bit. When SCANEN = 0, each time an A/D trigger occurs, the board will perform a single A/D conversion and then advance to the next channel and wait for the next trigger.

During interrupt operation, if FIFOEN = 1, then the FIFO will fill up with data until it reaches or exceeds half-full (half-full = 256 samples), and then the interrupt request will occur.

The basic sequence is as follows:

1.A/D trigger command occurs

2.A/D conversion or A/D scan occurs

3.A/D data is stored in the FIFO

4.Interrupt request occurs

5.Interrupt routine extracts data from the FIFO and resets the interrup request

A/D Trigger

The A/D trigger may come from one of three sources as determined by the control bits CLKEN and CLKSEL:

CLKEN

CLKSEL

A/D trigger source

0

0

Software command: write a 1 to ADSTART bit in register 8

0

1

Same as above

1

0

External signal: rising edge on EXTCLK pin on I/O header J3

1

1

Internal; counter/timer 0 controls the A/D conversion timing

A/D Conversion or Scan

Once the A/D trigger occurs, either a single A/D conversion will occur on the current channel, or an A/D scan will occur on a range of channels selected by the setting of register 2. The selection is made with the control bit SCANEN:

SCANEN Function

0Single conversion occurs on the current channel; The internal A/D channel counter increments after each conversion, so each successive trigger samples the next channel in the list. At the end of the list, the channel register resets to the starting channel and the sequence repeats.

1Scan occurs on all channels in the range programmed in the channel register (base + 2). The delay between the start of each conversion is determined by the setting of SCNINT in base + 9: SCNINT = 0 sets a delay of 5µs, and SCNINT = 1 sets a delay of 9.3µs.

Diamond-MM-48-AT User Manual V1.01

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Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing O Header Pinout and PIN Description Signal Name DefinitionJ3 Analog and Digital I/O J4 Relays and Optocouplers Signal Name Definition Relay output contactsOptoisolated input contacts Interrupt Level Selection Board ConfigurationBase Address Base Address Jumper Position Hex DecimalReserved Optocoupler PolarityAnalog Input Range Base + Write Function Read Function OverviewLSB MSB Read operations Register Map Bit AssignmentsWrite operations DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0Base + Read Register DefinitionsBase + Write DefinitionsBase + Read/Write A/D Channel Register AD9 AD8HIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 DIR3 DIR2 DIR1 DIR0 Base + Read/Write Digital I/O Configuration RegisterBase + Read/Write Relay Control Port RELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0 DIO3 DIO2 DIO1 DIO0Base + Read Digital I/O Data and Edge Status DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0Daupdt DACH2 DACH1 DACH0 Base + Write Channel and Control RegisterOEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Dapre Daprld Reset Fiforst Adstart Base + Write Command RegisterPOL ADCH3 ADCH2 ADCH1 ADCH0 Base + Read Status RegisterCKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Write Configuration RegisterAdbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Read Configuration & Status RegisterOVF Fifoth Fifoen Scanen Base + Write Fifo Control RegisterFifoth Fifoen Scanen Base + Read Fifo Status RegisterClrt Clrd Clro Clra Tinte Dinte Ointe Ainte Base + Write Interrupt Control RegisterTint Dint Oint Aint Tinte Dinte Ointe Ainte Base + Read Interrupt Status RegisterBase + Read/Write Counter/Timer D15 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D23 Ctrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Write Counter/Timer Control RegisterCtrno Base + Read/Write Eeprom / TrimDAC Address Register Base + Read/Write Eeprom / TrimDAC Data RegisterBase + Read Fpga Revision Code Base + Write Eeprom Access Key RegisterBase + Write Calibration Control Register Base + Read Calibration Status RegisterSingle Ended and Differential Inputs Analog Input Ranges and ResolutionResolution Input RangesPerforming AN A/D Conversion LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSB Trigger an A/D conversion on the current channelInput voltage = A/D value / 32768 * Full-scale voltage Conversion or Scan D SCAN, FIFO, and Interrupt OperationTrigger Clken ClkselFifoen = Fifo OperationInterrupt Operation Fifoen Fifoth ScanenOperation Table Guidelines for Selecting Fifo Use Fifoen and FifothAinte Fifoen Scanen Analog Output Overview Generating AN Analog Output 12.3 D/A Calibration Autocalibration OperationReference Voltages 12.2 A/D calibrationDigital I/O Operation Optocoupler Operation Procedure for enabling interrupts on selected edgesPolarity and logic readback Edge detection assumes OENn = 1 to enable edge detectionRelay Operation Counter 0 A/D Sample Control COUNTER/TIMER OperationCounter 1 Counting/Totalizing Functions Counter Command SequencesCounter Outpbase+15,0x01 Outpbase+15,0x81 Autocalibration SpecificationsGeneral
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