Diamond Power Products MM-48-AT user manual Base + Write Calibration Control Register

Page 26

Base + 14

Write

Calibration Control Register

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

EE_EN

EE_RW

RUNCAL

CMUXEN

TDACEN

 

 

 

 

 

 

 

 

 

 

 

 

This register is used to initiate various commands related to autocalibration. More detailed information on autocalibration may be found elsewhere in this manual.

EE_EN

EEPROM Enable. Writing a 1 to this bit will initiate a transfer to/from the

 

 

EEPROM as indicated by the EE_RW bit.

 

 

 

 

EE_RW

Selects read or write operation for the EEPROM: 0 = Write, 1 = Read.

 

RUNCAL

Writing 1 to this bit causes the board to reload the calibration settings from

 

 

EEPROM.

 

 

 

 

 

 

 

 

CMUXEN

Calibration multiplexor enable. The cal mux is used to read precision on-board

 

 

reference voltages that are used in the autocalibration process. It also can be

 

 

used to read back the value of analog output 0.

 

 

 

 

 

1 = enable cal mux and disable user analog input channels

 

 

 

 

0 = disable cal mux, enable user inputs

 

 

 

TDACEN

TrimDAC Enable. Writing 1 to this bit will initiate a transfer to the TrimDAC (used

 

 

in the autocalibration process).

 

 

 

 

 

 

Base + 14

Read

Calibration Status Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

 

7

6

5

 

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

0

TDBUSY

EEBUSY

 

CMUXEN

 

TDACEN

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

TDBUSY

TrimDAC busy indicator

 

 

 

 

 

 

0User may access TrimDAC

1TrimDAC is being accessed; user must wait

EEBUSY EEPROM busy indicator

0User may access EEPROM

1EEPROM is being accessed; user must wait

Base + 15

Write

EEPROM Access Key Register

The user must write the value 0xA5 (binary 10100101) to this register each time after setting the PAGE bit in order to get access to the EEPROM. This helps prevent accidental corruption of the EEPROM contents.

Base + 15

Read

FPGA Revision Code

This register may be read back to indicate the revision level of the FPGA code. The FPGA revision starts at 1 and increments up each time the code is revised.

Diamond-MM-48-AT User Manual V1.01

Page 26

Image 26
Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing J3 Analog and Digital I/O Signal Name DefinitionO Header Pinout and PIN Description Optoisolated input contacts Signal Name Definition Relay output contactsJ4 Relays and Optocouplers Base Address Jumper Position Hex Decimal Board ConfigurationBase Address Interrupt Level SelectionAnalog Input Range Optocoupler PolarityReserved LSB MSB OverviewBase + Write Function Read Function DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Register Map Bit AssignmentsWrite operations Read operationsDefinitions Register DefinitionsBase + Write Base + ReadHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 AD9 AD8Base + Read/Write A/D Channel Register RELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 Base + Read/Write Digital I/O Configuration RegisterBase + Read/Write Relay Control Port DIR3 DIR2 DIR1 DIR0DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 DIO3 DIO2 DIO1 DIO0Base + Read Digital I/O Data and Edge Status OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Channel and Control RegisterDaupdt DACH2 DACH1 DACH0 Base + Write Command Register Dapre Daprld Reset Fiforst AdstartBase + Read Status Register POL ADCH3 ADCH2 ADCH1 ADCH0Base + Write Configuration Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Configuration & Status Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Fifo Status Register Base + Write Fifo Control RegisterFifoth Fifoen Scanen OVF Fifoth Fifoen ScanenBase + Write Interrupt Control Register Clrt Clrd Clro Clra Tinte Dinte Ointe AinteBase + Read Interrupt Status Register Tint Dint Oint Aint Tinte Dinte Ointe AinteBase + Read/Write Counter/Timer D23 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D15 Ctrno Base + Write Counter/Timer Control RegisterCtrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Read/Write Eeprom / TrimDAC Data Register Base + Read/Write Eeprom / TrimDAC Address RegisterBase + Read Calibration Status Register Base + Write Eeprom Access Key RegisterBase + Write Calibration Control Register Base + Read Fpga Revision CodeInput Ranges Analog Input Ranges and ResolutionResolution Single Ended and Differential InputsPerforming AN A/D Conversion Trigger an A/D conversion on the current channel LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSBInput voltage = A/D value / 32768 * Full-scale voltage Clken Clksel D SCAN, FIFO, and Interrupt OperationTrigger Conversion or ScanFifoen Fifoth Scanen Fifo OperationInterrupt Operation Fifoen =Ainte Fifoen Scanen Guidelines for Selecting Fifo Use Fifoen and FifothOperation Table Analog Output Overview Generating AN Analog Output 12.2 A/D calibration Autocalibration OperationReference Voltages 12.3 D/A CalibrationDigital I/O Operation Procedure for enabling interrupts on selected edges Optocoupler OperationEdge detection assumes OENn = 1 to enable edge detection Polarity and logic readbackRelay Operation Counter 1 Counting/Totalizing Functions COUNTER/TIMER OperationCounter 0 A/D Sample Control Command Sequences CounterCounter Outpbase+15,0x01 Outpbase+15,0x81 General SpecificationsAutocalibration