Base + 9 | Write | Configuration Register |
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Bit No. |
| 7 |
| 6 |
| 5 | 4 |
| 3 | 2 | 1 | 0 |
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Name |
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| CKSEL1 | CKFRQ1 |
| CKFRQ0 | SCNINT | CLKEN | CLKSEL |
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CKSEL1 | Clock source select for counter/timer 1: |
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| 1 | External signal Clk0 in I/O connector J3 |
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| 0 |
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CKFRQ1 | Clock frequency select for counter/timer 1 when CKSEL1 = 0: |
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| 1 | 100KHz |
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| 0 | 10MHz |
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CKFRQ0 | Clock frequency select for counter/timer 0: |
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| 1 | 1MHz |
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| 0 | 10MHz |
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SCNINT | Scan interval. This is the time between A/D samples during an A/D scan. An A/D | |||||||||||
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| scan occurs when SCANEN = 1 (Base + 10 bit 4) and an A/D conversion is | ||||||||||
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| triggered. |
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| 1 | 5.0µS |
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| 0 | 9.3µS |
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CLKEN | Enable hardware A/D clock: |
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| 1 | Enable hardware A/D trigger (source is selected with CLKSEL bit); software | |||||||||
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| triggers are disabled |
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| 0 | Disable hardware trigger; A/D is triggered by setting the ADSTART bit |
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CLKSEL | A/D clock select, used only when CLKEN = 1: |
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| 1 | Internal clock: counter/timer 0 generates A/D conversions |
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| 0 | External clock: the EXTCLK pin on I/O connector J3, generates A/D | |||||||||
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| conversions |
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Page 18 |