Diamond Power Products MM-48-AT DIO3 DIO2 DIO1 DIO0, Base + Read Digital I/O Data and Edge Status

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Base + 5

Write

 

Digital I/O Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

DIO3

DIO2

DIO1

DIO0

 

 

 

 

 

 

 

 

 

 

 

Definitions:

DIO3 – 0 Digital I/O output data. Only bits in output mode are affected. Any bit in input mode will ignore data written to this register.

Base + 5

Read

Digital I/O Data and Edge Status

 

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Name

DEDGE3

DEDGE2

DEDGE1

DEDGE0

DIO3

DIO2

DIO1

DIO0

 

 

 

 

 

 

 

 

 

Definitions:

DEDGE3 – 0 Edge status for DIO lines: 1 = change occurred since last read, 0 = no change occurred

DIO3 – 0 Digital I/O readback. If a bit is in output mode, the readback value is equal to the programmed value.

Base + 6

Read/Write

Optocoupler Edge Detection Configuration Register

 

 

 

 

 

 

 

 

 

 

 

Bit No.

7

6

 

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Name

OEN3

OEN2

 

OEN1

OEN0

POL3

POL2

POL1

POL0

 

 

 

 

 

 

 

 

 

 

OEN3-0 Enable edge detection on the selected digital input line: 0 = disabled, 1 = enabled

POL3-0 Select active edge polarity for selected digital input line: 0 = falling, 1 = rising

An interrupt request will occur when OINTE = 1 and a digital input line enabled with OENn exhibits an edge whose polarity matches POLn (a qualifying edge). If an interrupt request occurs, and an additional qualifying edge occurs before the digital interrupt flip flop is reset, no additional interrupt request will be generated. It is possible for more than one line’s qualifying edge to be detected in a single interrupt (for example if 3 lines exhibit qualifying edges at the same time), but not more than one edge per line (for example if a second qualifying edge on the same line occurs before the interrupt is serviced).

It is possible for a qualifying edge to occur in the time between when the interrupt routine reads the digital input status register and when it resets the interrupt flip flop. In this case the qualifying edge will be lost, since resetting the flip flop also resets the edge detection status bits.

Diamond-MM-48-AT User Manual V1.01

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Image 14
Contents DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing J3 Analog and Digital I/O Signal Name DefinitionO Header Pinout and PIN Description Optoisolated input contacts Signal Name Definition Relay output contactsJ4 Relays and Optocouplers Base Address Jumper Position Hex Decimal Board ConfigurationBase Address Interrupt Level SelectionAnalog Input Range Optocoupler PolarityReserved LSB MSB OverviewBase + Write Function Read Function DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Register Map Bit AssignmentsWrite operations Read operationsDefinitions Register DefinitionsBase + Write Base + ReadHIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 AD9 AD8Base + Read/Write A/D Channel Register RELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 Base + Read/Write Digital I/O Configuration RegisterBase + Read/Write Relay Control Port DIR3 DIR2 DIR1 DIR0DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 DIO3 DIO2 DIO1 DIO0Base + Read Digital I/O Data and Edge Status OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0OEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Base + Write Channel and Control RegisterDaupdt DACH2 DACH1 DACH0 Base + Write Command Register Dapre Daprld Reset Fiforst AdstartBase + Read Status Register POL ADCH3 ADCH2 ADCH1 ADCH0Base + Write Configuration Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Configuration & Status Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken ClkselBase + Read Fifo Status Register Base + Write Fifo Control RegisterFifoth Fifoen Scanen OVF Fifoth Fifoen ScanenBase + Write Interrupt Control Register Clrt Clrd Clro Clra Tinte Dinte Ointe AinteBase + Read Interrupt Status Register Tint Dint Oint Aint Tinte Dinte Ointe AinteBase + Read/Write Counter/Timer D23 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D15 Ctrno Base + Write Counter/Timer Control RegisterCtrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Read/Write Eeprom / TrimDAC Data Register Base + Read/Write Eeprom / TrimDAC Address RegisterBase + Read Calibration Status Register Base + Write Eeprom Access Key RegisterBase + Write Calibration Control Register Base + Read Fpga Revision CodeInput Ranges Analog Input Ranges and ResolutionResolution Single Ended and Differential InputsPerforming AN A/D Conversion Trigger an A/D conversion on the current channel LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSBInput voltage = A/D value / 32768 * Full-scale voltage Clken Clksel D SCAN, FIFO, and Interrupt OperationTrigger Conversion or ScanFifoen Fifoth Scanen Fifo OperationInterrupt Operation Fifoen =Ainte Fifoen Scanen Guidelines for Selecting Fifo Use Fifoen and FifothOperation Table Analog Output Overview Generating AN Analog Output 12.2 A/D calibration Autocalibration OperationReference Voltages 12.3 D/A CalibrationDigital I/O Operation Procedure for enabling interrupts on selected edges Optocoupler OperationEdge detection assumes OENn = 1 to enable edge detection Polarity and logic readbackRelay Operation Counter 1 Counting/Totalizing Functions COUNTER/TIMER OperationCounter 0 A/D Sample Control Command Sequences CounterCounter Outpbase+15,0x01 Outpbase+15,0x81 General SpecificationsAutocalibration