AMD 8151 specifications Configuration spaces, Memory mapped address spaces, Register attributes

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

The following are configuration spaces:

Device

Function

Mnemonic

Registers

 

 

 

 

"A"

0

DevA:0xXX

AGP device header; link and AGP capabilities blocks

 

 

 

 

"B"

0

DevB:0xXX

PCI-PCI bridge registers for AGP

 

 

 

 

Table 3: Configuration spaces.

The IC does not claim configuration-register accesses to unimplemented functions within its devices (they are forwarded to the other side of the tunnel). Accesses to unimplemented register locations within implemented functions are claimed; such writes are ignored and reads always respond with all zeros.

The following are memory mapped spaces:

Base address

Size

Mnemonic

Registers

register

(bytes)

 

 

 

 

 

 

DevA:0x10

Variable

None

Graphic virtual memory aperture; minimum of 32 megabytes.

 

 

 

 

DevA:0xB8

4K

None

GART block in physical memory.

 

 

 

 

Table 4: Memory mapped address spaces.

The following are register attributes found in the register descriptions.

Type

Description

 

 

Read or read-only

Capable of being read by software. Read-only implies that the register cannot be written to by

 

software.

 

 

Write

Capable of being written by software.

 

 

Set by hardware

Register bit is set high by hardware.

 

 

Write once

After RESET#, these registers may be written to once. After being written, they become read only

 

until the next RESET# assertion. The write-once control is byte based. So, for example, software

 

may write each byte of a write-once DWORD as four individual transactions. As each byte is

 

written, that byte becomes read only.

 

 

Write 1 to clear

Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect.

 

 

Write 1 only

Software can set the bit high by writing a 1 to it. However subsequent writes of 0 will have no

 

effect. RESET# must be asserted in order to clear the bit.

 

 

Table 5: Register attributes.

5.2AGP Device Configuration Registers

These registers are located in PCI configuration space, in the first device (device A), function 0. See section 5.1.2 for a description of the register naming convention.

AGP Vendor And Device ID Register

DevA:0x00

Default: 7454 1022h

Attribute: Read only.

Bits

Description

 

 

 

 

31:16

AGP device ID.

 

 

 

 

15:0

Vendor ID.

 

 

 

 

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Contents AMD-8151TMDevice Device FeaturesOverview CoverAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Clock Gating Reset And InitializationFunctional Operation Overview ClockingTags, UnitIDs, And Ordering Tunnel LinksLink PHY AGPAGP Compensation And Calibration Cycles Translation from AGP requests to link requestsAGP transaction Link transaction Various BehaviorsAGP Device AGP Bridge Configuration SpaceRegisters Register Overview Register Naming and Description ConventionsConfiguration spaces Memory mapped address spacesRegister attributes REVISION. Read only AGP Device Status And Command Register DevA0x04RESET# AGP Device Revision and Class Code Register DevA0x08AGP Capabilities Pointer Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Device Subsystem ID and Subsystem Vendor ID RegisterDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl 1Fh, then 1Fh is applied 11b Updated by the hardware approximately every 8 microseconds1514 PctlHost translation#. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Bit Gart support. This bit fixed lowPcalcyc and then DevA0xB0CALDIS should be cleared afterward AGP Command RegisterDefault 0000 0000h Attribute Read-write RatesAGP Aperture Size Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Control RegisterSlave/primary interface type. Read only Link Command RegisterGarthi Gart base address register high Gartlo Gart base address register lowLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Must be high. See .3.1 for details ActlSum exceeds 1Fh, then 1Fh is applied 11b Clock Control RegisterAGP Bridge Revision and Class Code Register DevB0x08 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Vendor And Device ID Register DevB0x00AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Operating Ranges Absolute maximum ratingsOperating ranges Electrical Data Absolute RatingsSymbol Parameter Description Min Max Units Comments Current and power consumptionDC characteristics for signals on the VDD33 power plane DC CharacteristicsInput high voltage VDD15 + VDD15 AC data for clocks AC data for common clock operation of AGP signalsAC Characteristics Symbol Parameter Description Min Max UnitsAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationTest High Impedance ModeNand Tree Mode Test modesNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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