AMD 8151 specifications Default See below Attribute See below, Behavior 3021 Reserved 2016, Bctl

Page 28

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

Link PHY Compensation Control Registers

DevA:0x[E8, E4, E0]

 

 

The link PHY circuitry includes automatic compensation that is used to adjust the electrical characteristics for the link transmitters and receivers on both sides of the tunnel. There is one compensation circuit for the receiv- ers and one for each polarity of the transmitters. These registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. The overrides and difference values may be dif- ferent between sides A and B of the tunnel. These registers specify the compensation parameters as follows:

•DevA:0xE0: transmitter rising edge (P) drive strength compensation.

•DevA:0xE4: transmitter falling edge (N) drive strength compensation.

•DevA:0xE8: receiver impedance compensation.

For DevA:0x[E4, E0], higher values represent higher drive strength; the values range from 01h to 13h (19 steps). For DevA:0xE8, higher values represent lower impedance; the values range from 00h to 1Fh (32 steps).

Note: the default state of these registers is set by PWROK reset; assertion of RESET# does not alter any of the fields.

Default: See below.

Attribute: See below.

Bits

Description

 

 

 

31

Must be low. Read-write. This bit is required to be low at all times; setting it high results in undefined

 

behavior.

 

 

 

 

30:21

Reserved.

 

 

 

20:16

CALCCOMP: calculated compensation value. Read only. This provides the calculated value from

 

the auto compensation circuitry. The default value of this field is not predictable.

 

 

 

15

Reserved.

 

 

 

14:13

BCTL: link side B PHY control value. Read-write. These two bits combine to specify the PHY

 

compensation value that is applied to side B of the tunnel as follows:

 

BCTL

Description

 

00b

Apply CALCCOMP directly as the compensation value.

 

01b

Apply BDATA directly as the compensation value.

 

10b

Apply the sum of CALCCOMP and BDATA as the compensation value. In

 

 

DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the

 

 

sum exceeds 1Fh, then 1Fh is applied.

 

11b

Apply the difference of CALCCOMP minus BDATA as the compensation value. If the

 

 

difference is less than 01h, then 01h is applied.

 

The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If

 

CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b.

 

 

12:8

BDATA: link side B data value. Read-write. This value is applied to the side B of the tunnel PHY

 

compensation as described in BCTL. The default for DevA:0x[E4, E0] is 08h. The default for

 

DevA:0xE8 is 0Fh.

 

 

 

7

Reserved.

 

 

 

 

28

Page 27 Page 29
Image 28
Page 27 Page 29
Contents Device Features OverviewCover AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Power and Ground Test and Miscellaneous SignalsPower Plane Sequencing Reset And Initialization Functional Operation OverviewClocking Clock GatingTunnel Links Link PHYAGP Tags, UnitIDs, And OrderingTranslation from AGP requests to link requests AGP transaction Link transactionVarious Behaviors AGP Compensation And Calibration CyclesConfiguration Space Registers Register OverviewRegister Naming and Description Conventions AGP Device AGP BridgeMemory mapped address spaces Configuration spacesRegister attributes AGP Device Status And Command Register DevA0x04 RESET#AGP Device Revision and Class Code Register DevA0x08 REVISION. Read onlyDefault 0000 0000h Attribute Read write once Default 0000 00A0h Attribute Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register AGP Capabilities Pointer24888 Rev 3.03 July 12 Default 0000 0000h Attribute See belowAGP Miscellaneous Control Register DevA0x40 Nctl Updated by the hardware approximately every 8 microseconds 1514Pctl 1Fh, then 1Fh is applied 11bAGP Revision and Capability Register AGP Status RegisterBit Gart support. This bit fixed low Host translation#. This bit fixed lowAGP Command Register Default 0000 0000h Attribute Read-writeRates Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardDefault 0001 0F00h Attribute See below AGP3MD DrateAGP Control Register AGP Aperture Size RegisterLink Command Register Garthi Gart base address register highGartlo Gart base address register low Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 1 Register DevA0xD0 Link Frequency Capability 0 Register DevA0xCCLink Enumeration Scratchpad Register DevA0xD4 Behavior 3021 Reserved 2016 Default See below Attribute See belowBctl Actl Sum exceeds 1Fh, then 1Fh is applied 11bClock Control Register Must be high. See .3.1 for detailsAGP Bridge Configuration Registers AGP Bridge Status And Command Register DevB0x04AGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved Default 0000 00FFh Attribute See below DevB0x24. Default 0000 FFF0h Attribute Read-writeDevB0x3C Absolute maximum ratings Operating rangesElectrical Data Absolute Ratings Operating RangesCurrent and power consumption DC characteristics for signals on the VDD33 power planeDC Characteristics Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 AC data for common clock operation of AGP signals AC CharacteristicsSymbol Parameter Description Min Max Units AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingHigh Impedance Mode Nand Tree ModeTest modes TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
Top Page Image Contents