AMD 8151 specifications Test and Miscellaneous Signals, Power and Ground, Power Plane Sequencing

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

3.4 Test and Miscellaneous Signals

 

 

 

 

 

 

 

 

 

 

 

Pin name and description

 

IO cell

Power

During

After

 

 

type

plane

reset

reset

 

 

 

 

 

CMPOVR. Link automatic compensation override. 0=Link automatic compensation

Input

VDD33

 

 

is enabled. 1=The compensation values stored in DevA:0x[E0, E4, E8] control the

 

 

 

 

compensation circuit. The state of this signal determines the default value for

 

 

 

 

 

DevA:0x[E0, E4, E8][ACTL and BCTL] at the rising edge of PWROK.

 

 

 

 

 

 

 

 

 

 

 

FREE[7:1]. These should be left unconnected.

 

 

 

 

 

LDTSTOP#. Link disconnect control signal. This pin is also used for test-mode

Input

VDD33

 

 

selection; see section 9.

 

 

 

 

 

 

 

 

 

 

 

NC[1:0]. These should be left unconnected.

 

 

 

 

 

PWROK. Power OK. 1=All power planes are valid. The rising edge of this signal is

Input

VDD33

 

 

deglitched; it is not observed internally until it is high for more than 6 consecutive

 

 

 

 

REFCLK cycles. See section 4.2 for more details about this signal.

 

 

 

 

 

 

 

 

 

 

REFCLK. 66 MHz reference clock. This is required to be operational and valid for a

Input

VDD33

 

 

minimum of 200 microseconds prior to the rising edge of PWROK and always while

 

 

 

 

PWROK is high.

 

 

 

 

 

 

 

 

 

 

 

RESET#. Reset input. See section 4.2 for details.

 

Input

VDD33

 

 

 

 

 

 

 

STRAPL[19:13, 11:0]. Strapping option to be tied low. These pins should be tied to

IO

VDD15

3-State

3-State

ground. STRAPL0 is used for test-mode selection; see section 9.

 

 

 

 

 

 

 

 

 

 

 

STRAPL[22:20]. Strapping option to be tied low. These pins should be tied to

 

IO

VDD33

3-State

3-State

ground.

 

 

 

 

 

 

 

 

 

 

TEST. This is required to be tied low for functional operation. See section 9 for

Input

VDD33

 

 

details.

 

 

 

 

 

 

 

 

 

 

 

3.5 Power and Ground

VDD12[B, A]. 1.2 volt power plane for the HyperTransportTM technology pins. VDD12A provides power to the A side of the tunnel. VDD12B provides power to the B side of the tunnel.

VDD15. 1.5 volt power plane for AGP.

VDD18. 1.8-volt power plane for the core of the IC.

VDDA18. Analog 1.8-volt power plane for the PLLs in the core of the IC. This power plane is required to be filtered from digital noise.

VDD33. 3.3-volt power plane for IO.

VSS. Ground.

3.5.1Power Plane Sequencing

The following are power plane requirements that may imply power supply sequencing requirements.

•VDD33 is required to always be higher than VDD18, VDDA18, VDD15, and VDD12[B, A].

•VDD18 and VDDA18 are required to always be higher than VDD15 and VDD12[B, A].

•VDD15 is required to always be higher than VDD12[B, A].

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Contents Cover Device FeaturesOverview AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Power and Ground Test and Miscellaneous SignalsPower Plane Sequencing Clocking Reset And InitializationFunctional Operation Overview Clock GatingAGP Tunnel LinksLink PHY Tags, UnitIDs, And OrderingVarious Behaviors Translation from AGP requests to link requestsAGP transaction Link transaction AGP Compensation And Calibration CyclesRegister Naming and Description Conventions Configuration SpaceRegisters Register Overview AGP Device AGP BridgeMemory mapped address spaces Configuration spacesRegister attributes AGP Device Revision and Class Code Register DevA0x08 AGP Device Status And Command Register DevA0x04RESET# REVISION. Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Capabilities Pointer24888 Rev 3.03 July 12 Default 0000 0000h Attribute See belowAGP Miscellaneous Control Register DevA0x40 Nctl Pctl Updated by the hardware approximately every 8 microseconds1514 1Fh, then 1Fh is applied 11bBit Gart support. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Host translation#. This bit fixed lowRates AGP Command RegisterDefault 0000 0000h Attribute Read-write Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP Control Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Aperture Size RegisterGartlo Gart base address register low Link Command RegisterGarthi Gart base address register high Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 1 Register DevA0xD0 Link Frequency Capability 0 Register DevA0xCCLink Enumeration Scratchpad Register DevA0xD4 Behavior 3021 Reserved 2016 Default See below Attribute See belowBctl Clock Control Register ActlSum exceeds 1Fh, then 1Fh is applied 11b Must be high. See .3.1 for detailsAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved Default 0000 00FFh Attribute See below DevB0x24. Default 0000 FFF0h Attribute Read-writeDevB0x3C Electrical Data Absolute Ratings Absolute maximum ratingsOperating ranges Operating RangesDC Characteristics Current and power consumptionDC characteristics for signals on the VDD33 power plane Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 Symbol Parameter Description Min Max Units AC data for common clock operation of AGP signalsAC Characteristics AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingTest modes High Impedance ModeNand Tree Mode TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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